Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-16
2003-02-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06523159
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to integrated circuits. In particular, the present invention relates to a method for adding decoupling capacitance in an integrated circuit during the floor planning stage of integrated circuit design.
2. Related Art
One current trend in semiconductor design, especially for application specific integrated circuits (ASICs) and other advanced/complex semiconductor integrated circuit devices, such as microprocessors, is to lower the operating power. This trend drives power supply and device threshold (i.e., turn-on) voltages to lower levels. Another trend emphasizing the need for decoupling is that voltage scaling has lagged area/capacitance scaling. As the power grid supply voltage (VDD) and device threshold voltage (Vt) drop, the ratio of noise voltages to Vt and VDD increases, since noise levels do not scale down at the same rate as Vt and VDD. Consequently, sensitivity to noise in these types of semiconductor integrated circuit devices increases.
The increased sensitivity to noise is further exacerbated by local drops in VDD caused by local high current use. This may be caused, for example, by high current circuits or high duty cycle circuits. The effect is that some circuits or groups of circuits do not see the full VDD voltage for a short period of time, further increasing the noise to VDD ratio. Often, such a noise sensitivity problem does not become apparent until very late in the design process, or during actual device fabrication or testing, leading to expensive and time consuming remodeling, simulation, and/or design activity. Currently, the noise sensitivity problem is often overcome by over-designing the integrated circuits to make them more tolerant of noise or power drops. Unfortunately, this solution often results in decreased performance, increased power consumption, increased chip area, and more expensive chips.
One method of compensating for local power grid voltage drops is through the use of decoupling capacitors. The amount of decoupling capacitance required is a local requirement dependent upon such factors as the number of nearby circuits that are switching at one time and the sequence of the switching. The current state of the art accomplishes the task of adding decoupling capacitance to an integrated circuit design using one of two methods. In one method, the amount of decoupling capacitance per input/output (I/O) cell or clock buffer is estimated and then placed near the corresponding circuit. For the rest of the design, rule of thumb methods are used. One is to place the decoupling capacitors close to each latch. Another is to place decoupling capacitors on empty spaces in the chip area after placement. This often results in too much decoupling capacitance being added to the design. In another method, the amount of decoupling capacitance is calculated based on power drops in the grid voltage for the completed circuit as designed. Decoupling capacitors are then placed in those regions of the macros of the chip where there is space for them. One drawback of this method is that available space may not be close enough to where the decoupling capacitance is needed, requiring more decoupling capacitance to eliminate the voltage drop.
Thus, traditional methods of adding or placing decoupling capacitance in an integrated circuit often create other problems that can only be addressed after the design of an integrated circuit is complete. These include, inter alia,: wasted chip space and increased power requirements due to excess decoupling capacitance (and the support circuitry (e.g., switching buffer trees) required to implement the decoupling capacitance); and inadequate compensation for power drops in the grid voltage caused by the post-design placement of decoupling capacitance too far away from the circuit that requires it, increasing wiring requirements.
A need therefore exists for a method for adding decoupling capacitance during the design of an integrated circuit which solves these and other problems associated with currently available capacitance placement techniques.
SUMMARY OF THE INVENTION
The present invention provides a method for adding decoupling capacitance in an integrated circuit during the floor planning stage of integrated circuit design.
Generally, the present invention provides a method for adding decoupling capacitance in an integrated circuit design, comprising:
creating a floor plan for an integrated circuit, the floor plan comprising the relative locations of a plurality of functional units;
overlaying a power grid on the floor plan;
dividing the floor plan and the power grid into a plurality of regions; and, for each region:
determining a support decoupling capacitance value required to support a voltage of the power grid;
determining a native capacitance value;
determining a required decoupling capacitance value based on the support decoupling capacitance value and the native capacitance value;
determining a decoupling capacitor area for the required decoupling capacitance value; and
modifying a circuit area in the region based on the decoupling capacitor area.
The present invention additionally provides a method, comprising:
creating a floor plan for an integrated circuit;
dividing the floor plan into a plurality of regions; and, for each region:
determining a support decoupling capacitance value required to support a voltage of a power grid of the floor plan;
determining a native capacitance value;
determining a required decoupling capacitance value based on the support decoupling capacitance value and the native capacitance value;
determining a decoupling capacitor area for the required decoupling capacitance value; and
modifying a circuit area in the region based on the decoupling capacitor area.
The present invention further provides a computer program product, comprising:
a computer usable medium having a computer readable program code embodied therein for performing a method for adding decoupling capacitance in an integrated circuit design, the computer readable program code including:
code for causing a computer system to create a floor plan for an integrated circuit;
code for causing a computer system to divide the floor plan into a plurality of regions; and, for each region:
code for causing a computer system to determine a support decoupling capacitance value required to support a voltage of a power grid of the floor plan;
code for causing the computer system to determine a native capacitance value;
code for causing the computer system to determine a required decoupling capacitance value based on the support decoupling capacitance value and the native capacitance value;
code for causing the computer system to determine a decoupling capacitor area for the required decoupling capacitance value; and
code for causing the computer system to modify a circuit area in the region based on the decoupling capacitor area.
The foregoing and other features of the invention will be apparent from the following more particular description of the embodiments of the invention.
REFERENCES:
patent: 5761080 (1998-06-01), DeCamp et al.
patent: 5790839 (1998-08-01), Luk et al.
patent: 5883814 (1999-03-01), Luk et al.
patent: 5972740 (1999-10-01), Nakamori
patent: 6170079 (2001-01-01), Kato et al.
patent: 6323050 (2001-11-01), Dansky et al.
IBM Technical Disclosure Bulletin, vol. 38, No. 08, Aug. 1995, 1 page, Place Decoupling Capacitances in a Floor Plan.
Bernstein Kerry
Cohn John M.
Neves Jose L. P.
Kotulak Richard M.
Schmeiser Olsen & Watts
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