Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop
Reexamination Certificate
2001-01-12
2003-02-25
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Sequential or with flip-flop
C326S037000, C326S040000, C326S041000
Reexamination Certificate
active
06525565
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit input/output circuitry, and more particularly to a method and apparatus for doubling the rate at which registered data can be input to and output from an integrated circuit device.
BACKGROUND
In many digital logic applications it is desirable to present data at the input/output ports of an integrated circuit device (IC) employing as high a data rate as the IC device can tolerate. This high data throughput rate is important in applications such as network communications, cell phone base stations, and others.
Different approaches have been used in the past to maximize data input and output rates. Principal among these has been to speed up the clock rate at which a device is capable of operating. These approaches have focused on improving the process or manufacturing tolerances of the materials and tools used to make IC devices. However, whatever process or device improvements are made, for any given technology there is a maximum clock rate which sets the data rate.
Reprogrammable logic devices, such as field programmable gate arrays (“FPGA”), are commonly used in all types of digital logic applications. Consequently, FPGAs are used in many applications that require high data throughput. The data throughput rate of an FPGA, as with other ICs is also limited by its maximum clock rate.
FPGAs typically include an array of logic function generators or configurable logic elements, input/output ports, and a matrix of interconnect lines. The matrix of interconnect lines generally surrounds the configurable logic elements and connects logic data signals between the configurable logic elements and between the configurable logic elements and the input/output ports. FPGAs are configured by programming memory elements, such as static RAM cells; anti-fuses, EPROM cells, and EEPROM cells, which control configuration of the device. Depending on the programming of the memory elements, the configurable logic elements will perform different logic functions and be connected to each other and to the input/output ports in a variety of ways. In general, FPGA's also provide programmable memory cells to configure other features on the IC. For instance, the routing of clock signals and use of multiple clock nets on an FPGA is often programmably selectable by the user.
It is desirable then to implement a logic circuit design which, regardless of the limitations of the process used to manufacture an integrated circuit device, is capable of increasing the rate of data throughput at the device output for any given manufacturing process. It is further desirable to incorporate'such a logic circuit design into an FPGA to capitalize on the throughput capabilities of the logic circuit and to provide programmable features to the logic circuit design that cannot be provided in a nonconfigurable device.
SUMMARY OF THE INVENTION
In accordance with the present invention, a logic circuit design is disclosed that is capable of doubling the data throughput rate at the input/output port of an integrated circuit device for any given clock signal rate. This circuit may also be useful for intra-device communications. When the incorporated into an FPGA, the clock and data source used with the logic circuit may be programmably selectable. In a first aspect of the invention, a double data rate flip-flop comprised of two master latches and a multiplexer containing a slave latch is disclosed. Each master latch receives separate data signals and a clock signal that is substantially 180 degrees out of phase with the clock signal received by the other master latch. The output signal of each master latch is sent to the inputs of the multiplexer. The multiplexer also receives two clock signals 180 degrees out of phase with each other causing the multiplexer to alternate applying its inputs to its output and the slave latch synchronously with the clock signals. In a second separate aspect of the invention, the double data rate flip-flop circuitry can be optionally provided for an input path, an output path, and a tri-state enable path at a device input/output port. In a third separate aspect of the invention, the double data rate flip-flop circuitry can be programmably selected to operate as a double data rate flip-flop, a normal flip-flop, a latch, or an unregistered path. In a fourth separate aspect of the invention, when incorporated in an FPGA the clock source for the double data rate flip-flop can be programmably selected between a single clock and its inversion or two separate clocks synchronized to operate 180 degrees out of phase with each other, and the data source for the double data rate flip-flop may be programmably selected.
REFERENCES:
patent: 5844844 (1998-12-01), Bauer et al.
U.S. patent application Ser. No. 09/684,540, Young et al., filed Oct. 6, 2000.
Carberry Richard A.
Hassoun Joseph H.
Menon Suresh M.
Sodha Ketan
Young Steven P.
Brown Scott R.
Hovey Williams Timmons & Collins
Tokar Michael
Tran Anh Q.
Xilinx , Inc.
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