Semiconductor device, memory system, and electronic instrument

Details Semiconductor device, memory system, and electronic instrument Semiconductor device, memory system, and electronic instrument

2002-02-05

2003-11-25

Nguyen, Cuong Quang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S903000

Reexamination Certificate

active

06653696

ABSTRACT:

Japanese Patent Application No. 2001-34205, filed Feb. 9, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as an SRAM (Static Random Access Memory), and a memory system and an electronic instrument including the semiconductor device.
An SRAM is one type of semiconductor memory device which does not need refreshing. Therefore, the SRAM enables the system configuration to be simplified and consumes only a small amount of electric power. Because of this, the SRAM is suitably used as a memory for an electronic instrument such as portable telephones.
There has been a demand for miniaturization of portable equipment. To deal with this demand, the memory cell size of the SRAM must be reduced.
BRIEF SUMMARY OF THE INVENTION
An advantage of the present invention is to provide a semiconductor device enabling miniaturization of memory cells, and a memory system and an electronic instrument including the semiconductor device.
One aspect of the present invention provides a semiconductor device including a first gate—gate electrode layer located in a first conductive layer and including gate electrodes of a first load transistor and a first driver transistor and a second gate—gate electrode layer located in the first conductive layer and including gate electrodes of a second load transistor and a second driver transistor.
A first drain—drain connecting layer is located in a second conductive layer which is an upper layer of the first conductive layer and connects a drain of the first load transistor with a drain of the first driver transistor. A second drain—drain connecting layer is located in the second conductive layer and connects a drain of the second load transistor with a drain of the second driver transistor. A first drain-gate connecting layer is located in a third conductive layer which is an upper layer of the first and second drain—drain connecting layers and connects the first drain—drain connecting layer with the second gate—gate electrode layer and a stacked contact-conductive section connects the third conductive layer with the first conductive layer and has a structure in which an upper layer conductive section buried in a second interlayer dielectric used to insulate the second conductive layer from the third conductive layer is stacked over a lower layer conductive section buried in a first interlayer dielectric used to insulate the first conductive layer from the second conductive layer.


REFERENCES:
patent: 6404023 (2002-06-01), Mori et al.
patent: 6437455 (2002-08-01), Mori et al.
patent: 10-041409 (1998-02-01), None

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