Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-24
2003-02-25
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S645000, C438S680000, C438S692000, C438S639000
Reexamination Certificate
active
06524950
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89103124, filed Feb. 23, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating copper damascene. More particularly, the present invention relates to a method of fabricating multi-level metal interconnects.
2. Description of Related Art
As higher integration is required for integrated circuits, less chip surface area is available for interconnects fabrication. In order to be compatible with the requirement for increasing interconnects and minimizing metal-oxide-semiconductor (MOS) transistors, multi-level interconnect structures are widely used in the manufacture process of integrated circuits. To the latter parts of manufacture processes for semiconductor devices, the current density and the resistance of the metal line increase as the width of the metal line decreases. Therefore, the conventional metal line that is made of aluminum metal suffers from electromigration (EM), and reliability of the device is reduced. In place of aluminum, copper metal with lower resistance and less electromigration has become the major choice for semiconductor devices to solve the prior art problems.
Copper metal is widely used in metal interconnect fabrication because copper metal has many advantages, such as low resistivity, high melting points and high electromigration resistance. If copper metal is used in metal interconnects, instead of aluminum metal, the operation speed of the chip can be improved as much as doubled. Copper damascene is used to form copper metal interconnects, so that resistance-capacitance (RC) delay time and static charge capacity of metal interconnects can be reduced. Therefore, the trend is to use copper metal in metal interconnects in order to increase integration and conducting speed of the device.
However, copper metal can easily diffuse into material consisting of silicon and silicon oxide. Therefore, a barrier layer is deposited on the dielectric layer that is made of silicon oxide before the opening in the dielectric layer is filled with copper metal so that copper metal can no longer diffuse into the dielectric layer to cause a short in the device.
Furthermore, copper metal cannot be etched with conventional etching gases. Metal damascene is therefore used in the fabrication of copper metal interconnects. In metal damascene processes, an opening for a metal interconnect is etched first in a dielectric layer and the opening is filled with a metal material to form a metal interconnect. Because metal damascene satisfies the requirement of high reliability and high yield interconnects, metal damascene becomes the best choice for fabricating metal interconnects in sub-quarter micron processes.
In the prior art, after the opening in the dielectric layer is filled with copper metal, chemical mechanical polishing (CMP) is used to remove copper metal above the dielectric layer and outside the opening. Since copper metal is softer than aluminum metal, chemical mechanical polishing can cause severe dishing pits on the surface of metal lines; for example, a dishing pit deeper than 0.1 micron occurs in the copper metal line manufacture process of 0.8 to 1.0 micron.
FIGS. 1A and 1B
are schematic, cross-sectional views illustrating the fabrication processes of a copper damascene structure according to the prior art.
Referring to
FIG. 1A
, a dielectric layer
100
is defined to form a damascene trench
102
. A conformal barrier layer
104
is formed over dielectric layer
100
and damascene trench
102
. A conformal copper seed layer
106
is formed on conformal barrier layer
104
. A copper metal layer
108
is formed on conformal copper seed layer
106
and fills up damascene trench
102
.
Referring to
FIG. 1B
, chemical mechanical polishing with a pressure of about 300 to about 400 gw/cm
2
is used to sequentially remove copper metal layer
108
, conformal copper seed layer
106
and conformal barrier layer
104
above the surface of dielectric layer
100
. Copper damascene
108
a
, conformal copper seed layer
106
a
and conformal barrier layer
104
a
are formed thereon.
In the prior art, the copper seed layer is situated inside and outside the damascene trench; therefore, only a crystalline copper metal layer is formed. The crystalline copper metal layer has good lattice packing and is harder, so that higher pressure and the specific slurry for copper metal must be used in chemical mechanical polishing to remove the crystalline copper metal layer. Therefore, dishing pits are caused by the stress of chemical mechanical polishing in copper damascene according to the prior art.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating copper damascene. This method prevents dishing pits formation in the copper damascene.
The invention provides a method of fabricating copper damascene with chemical mechanical polishing. In addition to preventing the dishing pits from occurring in copper damascene, the cost of chemical mechanical polishing is also reduced.
The invention further provides a method of fabricating multi-level interconnects in the semiconductor devices. This invention provides a method of fabricating a flat-surfaced copper metal line.
As embodied and broadly described herein, the invention provides a method of fabricating copper damascene. A material layer containing a damascene trench is formed on a substrate. A conformal barrier layer that is made of, for example, tantalum nitride/tantalum, tantalum, titanium nitride or tungsten nitride, is formed to cover the damascene trench and the material layer. A conformal copper seed layer is formed on the conformal barrier layer. A photoresist layer is spin-coated to fill up the damascene trench and cover the conformal copper seed layer. A part of the photoresist layer and a part of the conformal copper seed layer that are outside the damascene trench are removed by chemical mechanical polishing until the conformal barrier layer outside the damascene trench is exposed. The remaining part of photoresist layer inside the damascene trench serves as protection for the conformal copper seed layer on the sidewalls of the damascene trench, to prevent the conformal copper seed layer being damaged by slurry employed in a chemical mechanical polishing step. After removing the photoresist damascene, a copper metal layer is formed on the conformal barrier layer and fills up the damascene trench. Chemical mechanical polishing with lower pressure is performed to remove the copper metal layer and the conformal barrier layer. A flat-surfaced copper damascene structure is formed inside the damascene trench.
This invention provides a method of fabricating copper damascene and for preventing dishing pits formation in the copper damascene. The pressure applied in the chemical mechanical polishing step to remove the copper metal layer and the conformal barrier layer is about 120 to about 240 gw/cm
2
, lower than that pressure used in the chemical mechanical polishing step in the prior art. Furthermore, the slurry used in the chemical mechanical polishing step is not specific for copper metal, so that the cost of the chemical mechanical polishing step is reduced. This invention can be used to form a flat-surfaced metal line in multi-level interconnects for semiconductor devices.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5354712 (1994-10-01), Ho et al.
patent: 5654245 (1997-08-01), Allen
patent: 5895261 (1999-04-01), Schinella et al.
patent: 6010962 (2000-01-01), Liu et al.
patent: 6093656 (2000-07-01), Lin
patent: 6162727 (2000-12-01), Schonauer et al.
patent: 6174811 (2001-01-01), Ding et al.
patent: 6287968 (2001-09-01), Yu et al.
Chaudhuri Olik
J.C. Patents
Maldonado Julio J.
Taiwan Semiconductor Manufacturing Co. Ltd.
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