Systems having shared memory and buses

Details Systems having shared memory and buses Systems having shared memory and buses

2000-02-17

2003-02-18

Dharia, Rupal (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S306000

Reexamination Certificate

active

06523082

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system having a boot ROM shared by a plurality of CPUs, and to a system having a PCI or AGP bus, etc., of which part is shared by the other busses.
2. Description of the Related Art
Typical systems utilizing computer graphics have often subjected a model consisting of a multiplicity of polygons to high-speed rendering and made use of a plurality of CPUs due to the need to move the model at a high speed. In such a case, for example, individual boot ROMs corresponding to the plurality of CPUs have stored respective activation programs dedicated to the respective CPUs. Otherwise, a single boot ROM linked to CPU busses have had segmented storage regions each storing an activation program dedicated to each CPU, for activation of each CPU.
FIG. 14
illustrates a schematic configuration of a conventional system having a plurality of boot ROMs linked to corresponding CPU busses. In this system, CPUs
1
to n are connected via CPU busses
21
to
2
n,
respectively, to bus bridges
11
to
1
n,
respectively. The bus bridges
11
to
1
n
are connected in tandem by way of PCI (peripheral component inter-contact) or AGP (accelerated graphics port) busses.
Then, the CPU busses
21
to
2
n
connect respectively to boot ROMs
61
to
6
n
each storing an activation program dedicated to the corresponding CPU in order to ensure that upon activation the CPUs can read the respective activation programs from the boot ROMs associated therewith.
FIG. 15
illustrates a schematic configuration of a conventional system having a plurality of boot ROMs coupled to corresponding bus bridges. In such a case, the boot ROMs
61
to
6
n
are connected via the bus bridges
11
to
1
n
to the CPUs
1
to n. In this case as well, the CPUs read the respective activation programs from the associated boot ROMS, for respective activations.
In case of coupling the boot ROMs
61
to
6
n
to the bus bridges
11
to
1
n,
respectively, as seen in
FIG. 15
, it is difficult to directly connect the boot ROMs
61
to
6
n
to the bus bridges
11
to
1
n
if the bus bridges
11
to
1
n
are bus bridges intended for the PCI or AGP bus. The following measures are thus taken.
For example, as shown in
FIG. 16
, a bus bridge
91
allowing connection of a bus
81
for boot ROM is provided and linked to the bus bridge
11
connecting the CPU bus
21
and a PCI or AGP bus
51
. Alternatively, as can be seen in
FIG. 17
, the bus bridge
11
connecting the CPU bus
21
and the PCI or AGP bus
51
is provided with a bus interface
92
allowing a connection of the bus
81
for boot ROM so that connection of the boot ROM
61
can be achieved through the bus interface
92
.
Although
FIGS. 16 and 17
depict the case where the boot ROM
61
is connected to the bus bridge
11
for PCI or AGP bus, the same applies to the case where other devices incapable of direct connection to the PCI or AGP bus are linked to the PCI or AGP bus.
However, use of individual boot ROMS for activations of a plurality of CPUs may result in an increased number of boot ROMs used, giving birth to a rise in system costs. Also, in the event of segmenting the storage area of a single boot ROM into a plurality of storage regions each storing therein an activation program dedicated to each CPU, the boot ROM must have a larger storage capacity, and connection of the boot ROM to the CPU busses may cause a greater load on the CPU busses at the time of activations, thus making it difficult to ensure a high-speed activation.
Furthermore, in order to connect the bus for boot ROM to the PCI or AGP bus, there is a need for a bus bridge dedicated to that application, resulting in a rise in system costs. In case of providing the bus bridge for PCI or AGP bus with the bus interface allowing connection of other busses, the bus bridge must have an increased number of pins, which will also result in a rise in the system costs.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a system including a plurality of CPUs which can be activated by a single boot ROM having a reduced storage area required.
Another object of the present invention is to reduce the number of pins of a bus bridge for PCI or AGP bus when any devices incapable of direct connection to a PCI or AGP bus are linked to the bus bridge for PCI or AGP, thereby to achieve a cutdown in costs of the system.
The above object is attained by providing a system having a plurality of CPUs connected to a plurality of corresponding bus bridges which are connected in tandem, wherein one of the plurality of bus bridges is associated with a memory which stores therein a common boot program for activating the plurality of CPUs in common, and individual boot programs for activating individually the plurality of CPUs, and wherein the CPU connected to the bus bridge associated with the memory gains access to the memory by accessing a predetermined address of the bus bridge, and wherein the remainder of the plurality of CPUs gain access to the same address as the predetermined address, of the bus bridges to which the remainder are respectively connected, the thus accessed bus bridge having access to the memory by accessing the same address as the predetermined address, of the other bus bridges adjacent toward the bus bridge associated with the memory.
According to the present invention, one of the plurality of bus bridges is associated with the memory which stores therein a common boot program for activating the plurality of CPUs in common and individual boot programs for individually activating the plurality of CPUS, whereby it is possible to share the single memory for activation by the plurality of CPUs in order to curtail the system costs.
According to the present invention, memory maps of the respective bus bridges are configured such that the adjoining bus bridges for access to the memory have the same address, so that memory maps of the respective CPUs can have the same memory address. Thus, a plurality of CPUs can be activated by a single memory in the system having the plurality of CPUs for execution of high-speed image processing, thereby achieving a cutdown in system costs. In addition, the memory is located at the same address in the respective memory maps of the plurality of CPUs, so that the programs are simplified with easy creation thereof.
According to the present invention, the single memory separately stores therein a common boot program common to the plurality of CPUs and individual boot programs, with the result that it is possible to reduce the storage area of the memory as well as to curtail the system costs.
The above object is achieved by providing a system having a CPU, a bus bridge connected to the CPU and connected via a predetermined bus to a predetermined device, and another device connectable to another bus different from the predetermined bus, wherein the another device is connected to the bus bridge by way of part of the predetermined bus, the CPU gaining access to the another device by way of part of the predetermined bus.
According to the present invention, part of a predetermined bus is used in common, for access to the other device connectable to another bus different from the predetermined bus, whereby the number of pins can remarkably be reduced as compared with the case where the bus bridges are each provided with an interface for another bus for direct connection to the other device, thus cutting down costs of the bus bridges and of the entire system.


REFERENCES:
patent: 5557757 (1996-09-01), Gephardt et al.
patent: 6081883 (2000-06-01), Popelka et al.
patent: 6266731 (2001-07-01), Riley et al.
Accelerated Graphics Port Interface Specification Revision 2.0, May 4, 1998, p. 20.

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