Coherency for DMA read cached data

Details Coherency for DMA read cached data Coherency for DMA read cached data

2000-08-24

2003-10-21

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000, C711S145000, C710S306000, C710S312000, C710S313000

Reexamination Certificate

active

06636947

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to information processing systems and more particularly to a methodology and implementation for enabling a coherency system for DMA read data in bridged systems.
BACKGROUND OF THE INVENTION
Computer Architectures generally allow implementations to incorporate such performance enhancing features as write-back caching, non-coherent instruction caches, pipelining, and out-of-order/speculative execution. These features introduce the concepts of coherency (the apparent order of storage operations to a single memory location as observed by other processors and DMA) and consistency (the order of storage accesses among multiple locations). In most cases, these features are transparent to software. However, in certain circumstances, operating system software explicitly manages the order and buffering of storage operations. By selectively eliminating ordering options, either via storage access mode bits or the introduction of storage barrier instructions, software can force increasingly restrictive ordering semantics upon its storage operations. Although the exemplary embodiment is directed toward a PowerPC platform, those skilled in the art will recognize that the following applies in general to other computer architectures.
PowerPC processor designs usually allow, under certain conditions, for caching, buffering, combining, and reordering in the platform's memory and I/O subsystems. These designs implement bus protocols which affect the memory access control and barrier operations that software uses to manage the order and buffering of storage operations. The platform's memory subsystem, system interconnect, and processors, which cooperate through a platform implementation-specific protocol to meet the PowerPC specified memory coherence, consistency, and caching rules, are said to be within the platform 's coherency domain. Bridges outside of the coherency domain cannot buffer DMA read data for an I/O adapter ahead of when the I/O adapter needs the data, otherwise the data in the bridge buffers outside of the coherency domain could get out of synchronization or non-consistent with the data in system memory.
PCI architecture provides a protocol for keeping data coherent when the I/O adapter's data are cached in the coherency domain of the system processors but not for data from the coherency domain that are buffered outside of the coherency domain.
Thus, there is a need for a method and implementing system which enables the maintenance of data coherency in systems which include data buffering beyond typical processor coherency domains.
SUMMARY OF THE INVENTION
A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which are accessed by adapters and adapter bridge circuits outside of the system coherency domains.


REFERENCES:
patent: 6138192 (2000-10-01), Hausauer
patent: 6138217 (2000-10-01), Hamaguchi
patent: 6199144 (2001-03-01), Arora et al.
patent: 6330630 (2001-12-01), Bell
patent: 013089 (2002-08-01), Weber

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