SRAM cell using thin gate oxide pulldown transistors

Details SRAM cell using thin gate oxide pulldown transistors SRAM cell using thin gate oxide pulldown transistors

1997-06-26

1999-08-17

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257401, 257903, G11C 1140

Patent

active

059397624

ABSTRACT:
The pulldown transistors of an SRAM cell are made to have higher threshold voltages and thinner gate insulating layers than the access transistors of the cell. In some embodiments, this allows a reduced supply voltage Vcc (for example, 3.3 volts) to be used in a reduced geometry (for example, 0.30-0.35 micron gate length) SRAM cell without reducing cell ratio, compromising cell stability, incurring oxide degradation from hot carrier injection or causing punch through problems. A mask is used to remove a first gate insulating layer from the pulldown transistor area and not from the access transistor area. In some embodiments, this same mask is then used to increase the threshold voltages of the pulldown transistors and not the access transistors by masking the access transistor areas from a shallow implant that increases transistor threshold voltage. After removing the mask, a second gate insulating layer is formed in both the pulldown and access transistor areas. As a result, the pulldown transistors of the SRAM cell have higher threshold voltages and thinner gate insulating layers than the access transistors of the cell.

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