Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-17
2003-12-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06658637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and an apparatus for trimming a semiconductor device which comprises at least a regular cell array, a spare cell array, a spare cell decoder for inhibiting selection of a plurality of cells on at least one row or column line in a regular cell array and for replacing the selected cells with a plurality of cells on at least one spare line in a spare cell array, and a fuse array including a plurality of fuses connected to the spare decoder. The present invention further relates to a method for creating a trimming table for use with the trimming method and apparatus.
2. Background Art
Many semiconductor devices such as memories generally comprise spare cell arrays in addition to their regular cell arrays. A spare cell array has at least one spare line and is used to replace a plurality of cells on at least one row or column line in a regular cell array that has failed.
The above type of semiconductor device comprises spare decoders and fuse arrays besides the regular and spare cell arrays. A spare decoder inhibits selection of a plurality of cells on a faulty row or column line in a regular cell array, and permits selection of a row or a column line in a spare cell array. A fuse array has a plurality of fuses, and generates command signals telling a spare decoder to inhibit selection of a regular cell array and to select a spare cell array in accordance with blow modes of the multiple fuses.
The blow modes of a fuse array correspond to blow patterns of a plurality of fuses included in that fuse array. As such, the blow modes correspond to address modes of an address signal for prompting selection of a row or a column line containing a faulty cell in a regular cell array.
In processes for fabricating the above type of semiconductor device, a trimming apparatus is used to blow a plurality of fuses in a given fuse array according to desired blow modes. Designed to blow fuses using laser in general, this apparatus is called a laser trimming apparatus. Of a plurality of fuses, only those designated are blown by the trimming apparatus. With conventional methods and apparatuses for trimming currently in use, it takes considerable time and effort to prepare programs for designating fuses to be blown.
Generally, tests performed on a semiconductor device yield data about faulty cells in its regular cell arrays. From the faulty cell data, addresses of rows or columns containing the faulty cells are derived. Blow modes corresponding to address modes of the addresses are obtained. Programs describing these specifics are then prepared manually.
A method improving on such conventional procedures is proposed illustratively by Japanese Patent Laid-open No. Hei 8-161385. The proposed method involves using a computer in support of writing programs. Because it includes special steps to name fuses in keeping with fuse layout data, the method remains fairly complicated.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a novel semiconductor device trimming method for trimming fuse arrays in a more simplified and generalized fashion than before.
It is another object of the present invention to provide an improved semiconductor device trimming apparatus for trimming fuse arrays in a more simplified and generalized manner.
It is a further object of the present invention to provide an innovative method for creating in a more simplified and generalized fashion a semiconductor device trimming table that is used to trim fuse arrays.
According to one aspect of the present invention, a semiconductor device trimming method is proposed for use with a semiconductor device. The semiconductor device includes a regular cell array, first and address lines, a spare cell array, a fuse array and a spare decoder. A regular cell array has a plurality of cells arranged in a matrix constituted by a plurality of first lines and by a plurality of second lines intersecting the first lines. First address lines select cells on each of the first lines in the regular cell array, and second address lines selects cells on each of the second lines in the regular cell array. A spare cell array has a plurality of cells arranged on at least one spare line corresponding to the first lines. A fuse array includes a plurality of fuses. A spare decoder is connected to the fuse array, and inhibits selection of cells on at least one of the first lines in the regular cell array in accordance with blow modes of the fuse array, and permit selection of cells on at least one of the spare lines in the spare cell array in order to replace the inhibited first line.
The semiconductor device trimming method is used selectively to blow fuses so as to impart the blow modes to the fuse array. In the semiconductor device trimming method, a trimming table is prepared which lists all address modes of address signals for the first address lines and the blow mode of the fuse array corresponding to each of the address modes. Then, fuses in the fuse array are selectively blown according to the blow mode corresponding to at least one of the first lines of which the selection has been inhibited in the regular cell array in accordance with the trimming table.
According to another aspect of the present invention, a semiconductor device trimming apparatus comprises storing means for storing a trimming table which lists all address modes of address signals for said first address lines and the blow mode of said fuse array corresponding to each of the address modes. The trimming apparatus further comprises blowing means for selectively blowing fuses in said fuse array in the blow mode corresponding to at least one of said first lines of which the selection has been inhibited in said regular cell array in accordance with said trimming table.
According to another aspect of the present invention, in a trimming table creating method, outputs of a logic circuits included in said spare decoder is monitored. Thereby, a trimming table is prepared which lists all address modes of address signals for said first address lines and the blow mode of said fuse array corresponding to each of the address modes.
Other features and advantages of the invention will be apparent from the following description taken in connection with the accompanying drawings.
REFERENCES:
patent: 5528372 (1996-06-01), Kawashima
patent: 5905681 (1999-05-01), Matsui
patent: 6108804 (2000-08-01), Derner
patent: 6349240 (2002-02-01), Ogawa et al.
patent: 8-161385 (1996-06-01), None
Fukushima Yasuhiko
Higashigawa Yoshihiro
Tanaka Masakazu
Bowers Brandon
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Siek Vuthe
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