Method for creating circuit redundancy in programmable logic...

Details Method for creating circuit redundancy in programmable logic... Method for creating circuit redundancy in programmable logic...

2001-04-13

2003-02-25

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C713S001000, C713S100000, C710S010000, C326S041000, C326S047000, C326S101000

Reexamination Certificate

active

06526559

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to programmable logic devices, and in particular to field programmable gate arrays (FPGA), either stand-alone FPGAs or “embedded” FPGAs (which include a non-configurable “hard-core” section and a dynamically reconfigurable “soft-core” section co-located on the same chip), in which the configurable logic blocks and the programmable routing structures are reconfigured dynamically and in which virtual redundancy is created for the purpose of fault tolerance of FPGAs.
In particular, the present invention relates to dynamically reconfigurable FPGAs where redundant circuits are created from structural elements of the FPGA unoccupied at a particular time period. In this fashion, a plurality of functionally identical duplicates of a primary circuit are created in a time multiplexing manner from structural elements of the unoccupied FPGA either by the primary circuit or by some duplicate circuits. For each application of the FPGA, the configured primary circuit and all duplicate circuits are interrogated by a voting circuit for detecting the presence of a fault, as well as for excluding a fault containing circuit (primary or any duplicate circuit) from operation.
Further, the present invention relates to a FPGA in which for fault tolerance thereof, no additional redundancy circuits need be added to the core structure of the FPGA, however, opposingly, the redundancy is created by dynamical reconfiguration of the structural elements of the FPGA in a time multiplexing manner. In this manner, identical circuits are formed, each in a respective time period, from unoccupied structural elements of the FPGA for further interrogation by a voting circuit for determining which of them is faulted and for excluding fault containing circuits from operation of the FPGA.
Also, the present invention relates to fault detection/diagnosis (isolation) in FPGAs by means of time multiplexing of a primary circuit and functional duplicates thereof configured from structural elements of FPGA in respective displaced time slots.
BACKGROUND OF THE INVENTION
Programmable logic devices include an array of configurable units, and by the nature of configuration of the configurable units for specific operation, may be divided into two groups, such as non-volatile and volatile programmable logic devices. The non-volatile programmable logic devices, in order to achieve a specific configuration of configurable units, require well-known “burn-in” techniques, and for this purpose they employ fusible links. Typically, these devices may only be configured once and do not allow for reconfiguration in different applications.
The volatile programmable logic devices, such as field programmable gate arrays (referred herein to as FPGAs), have found wide applicability due to the flexibility provided by their reprogrammable nature. Typically, as shown in
FIG. 1
, FPGA
10
has two internal chip layers, such as a foundation layer
12
where a static random access memory (SRAM) is created, and an upper layer
14
in which required circuitry is formed to perform desired logic functions. The upper layer
14
includes an array of configurable logic units that are programmably interconnected each to the other where each configurable logic unit may also be individually reprogrammed to perform a number of different logic functions. The upper layer
14
also includes a configurable routing structure for interconnecting the configurable logic units in accordance with the intended circuit application. The foundation layer
12
includes a plurality of configuration memory cells which are accessible through the application configuration port
16
through which an address of a memory cell to be accessed is input, and through which data exchange with the aimed memory cell is carried out. Since each bit of the static random access memory (SRAM) of the foundation layer
12
includes a flip-flop for recording a logical “1” or logical “0”, which may be set or reset an infinite number of times, on “power down” of the FPGA
10
, the state of the flip-flop is typically lost, thereby making the FPGA volatile.
The configuration memory cells of the SRAM are coupled to the upper layer
14
through the configuration data channel
18
to specify the function to be performed by each configurable logic unit as well as to specify the configurable routing structure between the logic units. Once a specific configurable circuit is formed in the upper layer
14
it is fed with user input data
20
to obtain user output data
22
at the output of the FPGA
10
.
As shown in
FIG. 2
, the SRAM in the foundation layer
12
is divided into three basic portions, (1) the logic unit configuration portion
24
which is devoted for programming the configurable logic units in the upper layer
14
; (2) the VIA configuration (interconnection) portion
26
which determines the routing structure of the FPGA; and, (3) the user flip-flops, latches, and memory portion
28
which includes data storage memory cells accessible by a user during operation of the FPGA. The VIA interconnections of the FPGA are controlled by a large number of multiplexers in the upper layer
14
.
Although the FPGA
10
shown in
FIGS. 1 and 2
have found wide applicability, they have drawbacks, which include relatively slow speed of reconfiguration (on the order of milliseconds) that has been found to be non-satisfactory for carrying out dynamic reconfiguration techniques, also known as “configuration on the fly”, which allows the promising concept of configuring a FPGA in stages in order to propagate a specific calculation. For example, in the prior art, if a Fast Fourier Transform is to be computed, and the entire Fast Fourier Transform network cannot be fit into an FPGA chip, the Fast Fourier Transform is partitioned into stages. Then, each stage of the Fast Fourier Transform is configured into the FPGA in a time sequence, and the results from stage to stage are stored in common memory or buffer. The results of a previous stage serve as input to a next page; and this process is repeated for all of the required stages of the Fast Fourier Transform. It will be clear to those skilled in the art that for such a dynamic configuration of the FPGA, a configuration time in a microsecond range would be highly advantageous.
Such dynamically reconfigurable FPGAs capable of being reconfigured within microseconds or less, have been developed by companies Xilinx, Inc., and Altera Corporation. For example, U.S. Pat. Nos. 5,978,260 and 6,105,105 describe FPGAs in which the complete configuration of FPGAs may be accomplished in less than one microsecond. These advanced FPGAs support dynamic configuration and time multiplexing by employing memory slices, as shown in FIG.
3
. Each memory slice
30
,
32
and
34
contains a complete configuration of the FPGA
10
for a specific function to be performed. By rapidly switching between different memory slices
30
,
32
and
34
through supply of “Select Slice” data
36
, the array of the configurable logic units in the upper layer
14
may be reconfigured from one application to another in a time multiplexing fashion. In the dynamically reconfigurable FPGAs shown in
FIG. 3
, the “logic unit configuration” portion
38
, “VIA configuration” portion
40
and “user flip-flops, latching and memory” portion
42
carry data in several channels, each corresponding to an active memory slice
30
,
32
or
34
.
Among numbers of applications thereof, FPGAs have found their use in aerospace applications where they are subject to radiation and cosmic particles. All semiconductor chips, including FPGAs, aboard a craft are vulnerable since the adverse space environment potentially causes intermittent faults, a.k.a. “Single Event Upset”, and permanent faults. Radiation and cosmic particles from space tend to inject electronic charge into the FPGA circuitry which may change the state of bistable elements or may cause an unwanted impulse on a gate. These faults are considered Single Event Upsets and represent the majority of radiation fa

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