Termination circuit with voltage-independent characteristics

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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Details

C326S086000

Reexamination Certificate

active

06515502

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the transistor-level termination circuit with voltage-independent characteristics.
2. Description of the Related Arts
In the design and implementation of electronic systems employing integrated circuits, undesired transmission line effect is of a particular concern. As the signal travels down to the transmission line, reflection may occur on the line. The reflection is caused by, for example the mismatched impedance between the driver circuit and the transmission line. If left uncorrected, the reflection may cause the signal's voltage to swing outside of the defined “0” and “1” voltage level. This causes the receiving device to incorrectly interpret the received signal and generate erroneous results.
To address the impedance mismatch between the driver and the transmission line or the receiver circuit and the transmission line, a variety of techniques have been known in the prior art. When it comes to compact size, low cost, the ability to be digitally trimmed as well as enabled or disabled by control signal, the most popular method is to use a MOS termination circuit.
FIG. 1
(
a
) shows a conventional MOS termination circuit using PMOSFET, while
FIG. 1
(
b
) shows another conventional MOS termination circuit using NMOSFET.
In
FIG. 1
(
a
), assume initially a low signal is asserted to the input node
125
to enable PMOSFET
120
before the driver
100
outputs a low signal to the transmission line
110
. When the PMOSFET
120
is turned on and driver
100
outputs low signal, the voltage levels of the drain node and the gate node of PMOSFET
120
are low. The PMOSFET
120
works in saturation region. When the driver
100
outputs high signal, the drain node of PMOSFET
120
is pulled high, and PMOS
120
operates in triode region. Therefore, during the pull-up process, the value of output impedance of PMOSFET
120
changes from high to low. To the contrary, during the pull-down process, the value of output impedance of PMOSFET
120
changes from low to high. The output impedance is voltage dependent. Similarly, the output impedance of circuit in FIG.
1
(
b
) is also voltage dependent.
SUMMARY OF THE INVENTION
It is therefore an objective of the invention to provide a voltage-independent MOS termination circuit that is easy to be implemented by today's MOS process.
It is yet another objective of the invention to provide a MOS termination circuit which includes a impedance compensation circuit.
The termination impedance circuit provided is coupled to a transmission line from a driver circuit. The termination impedance circuit includes a transistor-type resistor of a size A, and an impedance compensation circuit.
The transistor-type resistor of a size A is operative to receive a first control signal and has a node coupled to the transmission line.
The impedance compensation circuit includes a pair of transistors and a transistor of size B.
The pair of transistors has a first node inputting a second control signal, a second node connected to the transmission line, and a third node outputting a third control signal.
The transistor of a size B has a first node inputting the third control signal, and a second node connected to the transmission line.
The ratio of (A/B) is such that a substantial constant output impedance is achieved as large pull-down or pull-up voltage excursion at the transmission line occurs.


REFERENCES:
patent: 5382847 (1995-01-01), Yasuda
patent: 6054881 (2000-04-01), Stoenner
patent: 0327160 (1989-08-01), None

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