Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-06-22
2003-11-18
Wojciechowicz, Edward (Department: 2815)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S216000, C438S261000, C438S769000, C438S775000, C438S791000, C257S288000
Reexamination Certificate
active
06649543
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of forming silicon nitride, and particularly pertains to methods of forming silicon nitride over silicon-oxide-comprising materials. The invention also pertains to methods of forming transistor devices, and further pertains to transistor device structures.
BACKGROUND OF THE INVENTION
There are numerous semiconductor processing applications in which it is desired to form a silicon-nitride-comprising layer over a silicon-oxide-comprising layer. For instance, it can be desired to form transistor devices having silicon nitride and silicon oxide as dielectric materials between a conductive gate and a channel region. A difficulty in forming silicon nitride over silicon oxide is described with reference to
FIGS. 1 and 2
.
Referring initially to
FIG. 1
, a top view of a fragment of a semiconductor structure is shown. Fragment
10
comprises an oxide surface
12
upon which nitride
14
is to be formed. Oxide surface
12
can comprise, for example, silicon dioxide; and nitride
14
can comprise, for example, silicon nitride (Si
3
N
4
). The silicon nitride can be deposited by, for example, chemical vapor deposition. A problem is that the silicon nitride does not deposit readily on silicon dioxide, because there are only a few bonds available for bonding of nitrogen to silicon in silicon dioxide. Accordingly, the silicon nitride forms in small localized islands. The islands grow, and eventually merge to form a silicon nitride surface
14
that entirely covers silicon oxide
12
. Such silicon nitride surface is shown in FIG.
2
.
The silicon nitride material that ultimately forms the surface of
FIG. 2
will typically be from about 30 to 35 Å thick, and will frequently be non-uniform in thickness as it was formed from the merger of relatively thick islands (frequently the islands are about 28 Å thick when they merge) so that the portions where edges of the islands merged are thinner than portions corresponding to centers of the islands. Further, it can be difficult to control the overall thickness of nitride material
14
, as it is difficult to control how thick the islands of
FIG. 1
will be when they finally merge.
It would be desirable to develop new methods of forming silicon nitride which overcome some or all of the above-discussed problems.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a method of forming silicon nitride on a silicon-oxide-comprising material. The silicon-oxide-comprising material is exposed to activated nitrogen species from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the material. The nitrogen is thermally annealed within the material to bond at least some of the nitrogen to silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the material.
In another aspect, the invention encompasses a method of forming a transistor device. A silicon-oxide-comprising layer is formed over a substrate. The silicon-oxide-comprising layer is exposed to activated nitrogen from a nitrogen-containing plasma to introduce nitrogen into an upper portion of the layer. The nitrogen is thermally annealed within the layer to bond at least some of the nitrogen to silicon proximate the nitrogen. After the annealing, silicon nitride is chemical vapor deposited on the nitrogen-containing upper portion of the layer. At least one conductive gate layer is formed over the silicon nitride, and defines a gate layer. A pair of source/drain regions are formed proximate the gate layer and gatedly connected to one another through a channel region that is beneath the gate layer.
In yet another aspect, the invention encompasses transistor device structures.
REFERENCES:
patent: 5026574 (1991-06-01), Economu et al.
patent: 5032545 (1991-07-01), Doan et al.
patent: 5164331 (1992-11-01), Lin et al.
patent: 5254489 (1993-10-01), Nakata
patent: 5258333 (1993-11-01), Shappir et al.
patent: 5318924 (1994-06-01), Lin et al.
patent: 5330920 (1994-07-01), Soleimani et al.
patent: 5378645 (1995-01-01), Inoue et al.
patent: 5382533 (1995-01-01), Ahmad et al.
patent: 5436481 (1995-07-01), Egawa et al.
patent: 5445999 (1995-08-01), Thakur et al.
patent: 5449631 (1995-09-01), Giewont et al.
patent: 5464792 (1995-11-01), Tseng et al.
patent: 5518946 (1996-05-01), Kuroda
patent: 5518958 (1996-05-01), Giewont et al.
patent: 5596218 (1997-01-01), Soleimani et al.
patent: 5612558 (1997-03-01), Harshfield
patent: 5619057 (1997-04-01), Komatsu
patent: 5620908 (1997-04-01), Inoh et al.
patent: 5633036 (1997-05-01), Seebauer et al.
patent: 5663077 (1997-09-01), Adachi et al.
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5685949 (1997-11-01), Yashima
patent: 5716864 (1998-02-01), Abe
patent: 5719083 (1998-02-01), Komatsu
patent: 5760475 (1998-06-01), Cronin
patent: 5763922 (1998-06-01), Chau
patent: 5834372 (1998-11-01), Lee
patent: 5885877 (1999-03-01), Gardner et al.
patent: 5939750 (1999-08-01), Early
patent: 5960289 (1999-09-01), Tsui et al.
patent: 5960302 (1999-09-01), Ma et al.
patent: 5970345 (1999-10-01), Hattangady et al.
patent: 5972783 (1999-10-01), Arai et al.
patent: 5972800 (1999-10-01), Hasegawa
patent: 5994749 (1999-11-01), Oda
patent: 5998253 (1999-12-01), Loh et al.
patent: 6033998 (2000-03-01), Aronowitz et al.
patent: 6054396 (2000-04-01), Doan
patent: 6057220 (2000-05-01), Ajmera et al.
patent: 6080629 (2000-06-01), Gardner et al.
patent: 6080682 (2000-07-01), Ibok
patent: 6087229 (2000-07-01), Aronowitz et al.
patent: 6091109 (2000-07-01), Hasegawa
patent: 6091110 (2000-07-01), Herbert et al.
patent: 6093661 (2000-07-01), Trivedi et al.
patent: 6110842 (2000-08-01), Okuno et al.
patent: 6114203 (2000-09-01), Ghidini et al.
patent: 6136636 (2000-10-01), Wu
patent: 6140187 (2000-10-01), DeBusk et al.
patent: 6146948 (2000-11-01), Wu et al.
patent: 6174821 (2001-01-01), Doan
patent: 6184110 (2001-02-01), Ono et al.
patent: 6197701 (2001-03-01), Shue et al.
patent: 6201303 (2001-03-01), Ngo et al.
patent: 6207532 (2001-03-01), Lin et al.
patent: 6225167 (2001-05-01), Yu et al.
patent: 6228701 (2001-05-01), Dehm et al.
patent: 6232244 (2001-05-01), Ibok
patent: 6255703 (2001-07-01), Hause et al.
patent: 6268296 (2001-07-01), Misium et al.
patent: 6274442 (2001-08-01), Gardner et al.
patent: 6323114 (2001-11-01), Hattangady et al.
patent: 6331492 (2001-12-01), Misium et al.
patent: 6362085 (2002-03-01), Yu et al.
patent: 6399445 (2002-06-01), Hattangady et al.
patent: 6399448 (2002-06-01), Mukhopadhyay et al.
patent: 6410991 (2002-06-01), Kawai et al.
patent: 6482690 (2002-11-01), Shibata
patent: 6492690 (2002-12-01), Ueno et al.
patent: 2003/0034518 (2003-02-01), Yohikawa
patent: WO 96/39713 (1996-12-01), None
Doyle, B. et al., “Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing”, IEEE vol. 16 (7), Jul. 1995, pp. 301-302.
Kuroi, T. et al., “The Effects of Nitrogen Implantation Into P+Poly-Silicon Gate on Gate Oxide Properties”, 1994 Sympos. on VLSI Technology Digest of Technical Papers, IEEE 1994, pp. 107-108.
Liu, C.T. et al., “Multiple Gate Oxide Thickness for 2GHz System-on-a-Chip Technologies”, IEEE 1998, pp. 589-592.
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