Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-27
2003-11-18
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S305000, C257S321000
Reexamination Certificate
active
06649956
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuit devices and manufacturing architectures of the same. More particularly, but not exclusively, the invention relates to those technologies which are adaptable for use with semiconductor integrated circuit devices having dynamic random access memory (“DRAM”) modules.
BACKGROUND OF THE INVENTION
Currently available DRAMs are typically designed to include an array consisting of rows and columns of memory cells disposed in a matrix form on a principal surface of a semiconductive substrate at cross points or “intersections” between a plurality of word lines and a plurality of bit lines, wherein each of the memory cells consists essentially of a capacitive element for accumulation of information and a metal insulator semiconductor field effect transistor (MISFET) for use in selecting a single memory cell, which MISFET is serially connected to the capacitive element. The memory cell selecting MISFET is formed in an active region of the semiconductor substrate which is surrounded at its periphery by an element separation or isolation region. The MISFET is generally designed to consist of a gate oxide film and a gate electrode integral with a corresponding one of the word lines, plus a pair of semiconductor active regions for use as a source and drain of the transistor. A bit line is disposed to overlie the memory cell selecting MISFET in a manner such that it is electrically connected to one of the source and drain which is commonly shared by two memory cell selection MISFETS. The information accumulation capacitive element is laid out at a location overlying the memory cell select MISFET and is electrically coupled to the remaining one of the source and drain.
A DRAM device having a memory cell structure of this type has been disclosed in Published Unexamined Japanese Patent Laid-Open No. 5-291532 and other publications. The memory cells of the DRAM as disclosed therein are designed so that word lines are increased in width or made “fat” in active regions (the regions in each of which a word line serves as the gate electrode of a memory cell select MISFET) and reduced in width or “thinned” in the remaining regions in order to retain the required gate length when miniaturizing or “downsizing” the memory cell select MISFETs, while at the same time minimizing the pitch of word lines.
In addition, the DRAM memory cells as described by the Japanese Application referred to above is arranged so that the bit lines are partly fattened to extend up to those portions overlying the active regions and a planar pattern of such active regions is designed into a gull-wing shape with part of it being bent toward the bit line side in order to achieve successful electrical conduction of more than one contact hole for use in connecting between one of the source and drain of a memory cell select MISFET and its corresponding bit line operatively associated therewith.
Regrettably the DRAM memory cells described by the above Japanese Application has the inherent problem of being unable to provide any excellent size/dimension accuracy when partly increasing the widths of word lines and bit lines or when employing the gullwing-shaped planar pattern of the active regions, due to the fact that presently available photolithography techniques suffer from difficulties in accurately achieving ultra-fine resolution of curved-line patterns and/or folded-line patterns in cases where the minimal fabricatable size becomes at or near a limit of resolution in photolithography processes as a result of further progress in microfabrication or miniaturization of such memory cells. Another problem inherent in the prior art DRAM device is that as a through-going hole for use in connecting between the lower-side electrode of an information accumulation capacitive element and the remaining one of the source and drain of its associated memory cell select MISFET is inherently disposed between one bit line and another bit line, so that partly fattening the bit lines makes it difficult to attain the intended through-hole opening margin, which leads to an inability to assure elimination of unwanted electrical short-circuiting between the lower-side electrode within a though-hole and its associative one of the bit lines.
It is therefore an object of the present invention to provide a specific technique for enabling achievement of further miniaturization of memory cells of a DRAM.
The foregoing and other objects and inventive features of this invention will become more apparent from the following description and accompanying drawings.
SUMMARY OF THE INVENTION
Some representative aspects of the present invention as disclosed herein will be explained in brief below.
(1) A semiconductor integrated circuit device incorporating the principles of the invention is arranged to have a plurality of word lines extending in a first direction on a principal surface of a semiconductive substrate, a plurality of bit lines extending in a second direction at right angles to the first direction, and an array of memory cells of a DRAM as disposed at cross points of said word lines and said bit lines, each said memory cell including a serial combination of a memory cell selecting MISFET with a gate electrode integrally formed with a corresponding one of said word lines and a capacitive element for information accumulation, wherein said plurality of word lines are arranged to linearly extend in the first direction on the principal surface of said semiconductive substrate with an identical width, and wherein a distance between adjacent ones of said word lines is less than said width.
(2) The semiconductor integrated circuit device of the invention is formed such that the distance between the adjacent ones of said gate electrodes is set at a minimal size as determined by a resolution limit of photolithography.
(3) The semiconductor integrated circuit device of the invention is formed such that said word lines and the gate electrode of said memory cell selecting MISFET integrally formed with a corresponding one of said word lines are comprised of a conductive film at least partially including a metallic film therein.
(4) The semiconductor integrated circuit device of the invention is formed such that said semiconductive substrate has an active region with said memory cell selecting MISFET formed therein and being arranged to have an island-like pattern extending in the second direction on the principal surface of said semiconductive substrate while having its periphery surrounded by an element isolation region.
(5) The semiconductor integrated circuit device of the invention is formed such that the element isolation region surrounding said active region is formed of an element separation groove having a dielectric film embedded therein as defined in the principal surface of said semiconductive substrate.
(6) The semiconductor integrated circuit device of the invention is formed such that said bit lines are formed to overlie said memory cell selecting MISFET with an insulative film laid therebetween, wherein a contact hole for electrical connection between one of a source and drain of said memory cell selecting MISFET and a corresponding one of said bit lines is formed in self-alignment with the gate electrode of said memory cell selecting MISFET.
(7) The semiconductor integrated circuit device of the invention is formed such that said information accumulation capacitive element is formed to overlie said memory cell selecting MISFET with an insulative film laid therebetween, wherein a contact hole for electrical connection between the other of the source and drain of said memory cell selecting MISFET and one electrode of said information accumulation capacitive element is formed in self-alignment with the gate electrode of said memory cell selecting MISFET.
(8) The present invention also provides a semiconductor integrated circuit device comprising a plurality of word lines extending in a first direction on a principal surface of a semiconductive substrate, a plurality of
Asano Isamu
Hasegawa Norio
Kawakita Keizo
Kumauchi Takahiro
Tadaki Yoshitaka
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Wojciechowicz Edward
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