Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2002-09-05
2003-02-11
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S113000, C711S148000, C710S313000, C710S316000
Reexamination Certificate
active
06519680
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a controller of a disk array apparatus which stores data on multiple hard disk drives.
As compared with the computer main storage which is based on the semiconductor memory, the disk subsystem (will be termed simply “subsystem”) which is based on the magnetic disk memory is sluggish in regard to the I/O performance by a degree of the order of 3-4 digits, and continuous efforts have been paid to reduce the difference of these memories, i.e., improve the I/O performance of the subsystem.
A known scheme to improve the I/O performance of the subsystem is the adoption of a disk array system in which multiple hard disk drives are organized to form a subsystem, and data is stored on the multiple hard disk drives.
For example, a prior art system shown in
FIG. 2
includes multiple channel IF units
11
which implement the data transfer between host computers
50
and disk array controllers
2
, multiple disk IF units
12
which implement the data transfer between magnetic disk drives
5
and disk array controllers
2
, cache memory units
14
which temporarily store data of the hard disk drives
5
, and shared memory units
13
which store control information for the disk array controllers
2
(e.g., information on data transfer control between the channel IF units
11
and disk IF units
12
and the cache memory units
14
and control information for data stored in the hard disk drives
5
). In each disk array controller
2
, the shared memory unit
13
and cache memory unit
14
can be accessed by all channel IF units
11
and disk IF units
12
.
In the disk array controller
2
, the channel IF units
11
and disk IF units
12
are connected to the shared memory unit
13
by an interconnection
21
, and the channel IF units
11
and disk IF units
12
are connected to the cache memory unit
14
by another interconnection
22
.
The channel IF unit
11
has the interface for the connection to host computers
50
and a microprocessor (not shown) which controls the data transaction with the host computers
50
. The disk IF unit
12
has the interface for the connection to hard disk drives
5
and a microprocessor (not shown) which controls the data transaction with the hard disk drives
5
. The disk IF units
12
have the RAID function.
This conventional disk array controller
2
has an upper limit of disk storage capacity which can be connected to it, and therefore for storing data in excess of the volume of data manageable by one disk array controller
2
, multiple disk array controllers
2
are installed and channels from the host computers
50
are connected to the disk array controllers
2
. Furthermore, for connecting host computers
50
in excess of the number of host channels which can be connected to one disk array controller
2
, multiple disk array controllers
2
are installed and connected to the host computers
50
individually.
For data transfer between two disk array controllers
2
, channels from the host computers
50
are connected to the two disk array controllers
2
and data is transferred via the host computers
50
.
Another prior art system shown in
FIG. 3
, which is disclosed in U.S. Pat. No. 5,680,640, is designed for example to transfer data between two disk array controllers
3
based on the connection of part (two lines in
FIG. 3
) of the computer interface paths of the disk array controllers
3
and the data transfer from a hard disk drive
5
which is connected to one disk array controller
3
to another hard disk drive
5
which is connected to another disk array controller
3
through the data transfer path
8
.
Another prior art system shown in
FIG. 4
is designed for example to store data in excess of the volume of data manageable by one disk array controller, connect host computers in excess of the number of host channels which can be connected to one disk array controller, or transfer data among multiple disk array controllers, as shown in
FIG. 4
, based on the installation of multiple disk array controllers
4
and the connection of their computer interface paths to the host computers
50
via a switch-based interconnection
23
.
A disk array processing device disclosed in Japanese Unexamined Patent Publication No. Hei-11-66693 includes two director units which use a shared memory to recover data when a data spindle which forms a disk array runs out of control. This patent publication, however, does not show the installation of multiple disk arrays.
In large business enterprises which typically include banks, stock traders, and telephone companies, there are trends of cutting the expenditure for the operation, maintenance and management of computer systems and storage systems based on the centralized installation of computers and storages which have been installed distributively in many places. In this movement with the times, large high-end disk array controllers are required to bear the channel interface for the connection to several-hundreds or more host computers and huge storage capacities of several-hundreds terabytes or more.
At the same time, due to growing open markets in recent years and storage area networks (SANs) which are expected to prevail in coming years, there are rising demands of small-scale (compact) disk array controllers which are comparable in performance and reliability with large high-end disk array controllers.
The former requirement will conceivably be met by connecting multiple conventional large high-end disk array controllers to build a huge disk array controller. The latter requirement will conceivably be met by arranging a lowest-level model (e.g., with small numbers of channel IF units and disk IF units) of a conventional large high-end disk array controller. An additional conceivable scheme is to connect a plurality of this compact disk array controller thereby to build a controller which supports systems of medium to large scales which have been supported by a conventional disk array controller.
Accordingly, it becomes necessary for disk array controllers to have the scalability so as to be constructed to cover the range from a small to huge-scale controllers based on the same basic architecture of high performance and high reliability, and therefore there arises a demand of a disk array controller, a plurality of which are integrated to operate as a single disk array controller.
However, although the prior art system shown in
FIG. 2
can have an increased number of channels and increased storage capability for the host computers
50
by simply increasing the number of disk array controllers
2
, the host computers
50
need to connect channels to all disk array controllers
2
so that one host computer
50
can transact data with multiple disk array controllers
2
. Moreover, it is necessary for one host computer
50
which is going to make access to data to identify a disk array controller
2
that is connected to the hard disk drive
5
which stores the data. On this account, it is difficult to operate multiple disk array controllers as a single disk array controller.
The prior art system shown in
FIG. 3
has disk array controllers
3
interconnected by the data transfer path
8
, enabling one host computer
50
which is connected to a certain disk array controller
3
to make access to data on a hard disk drive
5
which is connected to other disk array controller
3
, and accordingly it is possible to operate multiple disk array controllers
3
as a single disk array controller.
However, in case a host computer
50
issues a data read request to a disk array controller
3
and the data is absent on the hard disk drives
5
connected to the controller
3
, it is necessary for the disk array controller
3
to send the read request to other disk array controller
3
over the data transfer path
8
, receive the requested data over the data transfer path
8
from the disk array controller
3
which is connected to the hard disk drive
5
on which the data is stored, and send the requested data to the host computer
50
. On this account, this syste
Fujibayashi Akira
Fujimoto Kazuhisa
Kanai Hiroki
Sakurai Wataru
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nguyen Hiep T.
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