Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-21
2003-10-21
Thompson, Craig (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06635938
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof and, more specifically, to a semiconductor device in which electrical insulation of a transistor is ensured, as well as to the manufacturing method thereof.
2. Description of the Background Art
A method of manufacturing a semiconductor device including an MOS transistor, as an example of a conventional semiconductor device, will be described with reference to the figures, First, referring to
FIG. 23
, a trench element isolating film
102
for forming an element forming region is formed on a silicon substrate
101
. Thereafter, a thermal oxide film (not shown) is formed on a surface of silicon substrate
101
by thermal oxidation.
On the thermal oxidation film, a polycrystalline silicon film and a silicon oxide film (both not shown) are formed by the CVD method. On the silicon oxide film, a prescribed photoresist pattern (not shown) is formed. Using the photoresist pattern as a mask, the silicon oxide film, the polycrystalline silicon film and the thermal oxide film are anisotropically etched, so that a gate oxide film
106
, a polysilicon gate
107
and a silicon oxide film
108
are formed.
Thereafter, as shown in
FIG. 24
, a silicon oxide film
109
is formed by the CVD method on silicon substrate
101
to cover polysilicon gate
107
and the like. Thereafter, as shown in
FIG. 25
, silicon oxide film
109
is anisotropically etched, so as to form sidewall oxide films
109
a
on the side surfaces of polysilicon gate
107
.
Thereafter, as shown in
FIG. 26
, an impurity producing a prescribed conductivity type is introduced by ion implantation into the surface of silicon substrate
101
. Further, by heat treatment, a pair of source and drain regions
111
a
and
111
b
are formed.
Thereafter, referring to
FIG. 27
, silicon films
112
a
and
112
b
are formed selectively only on the surfaces of source and drain regions
111
a
and
111
b
by selective epitaxial growth. Thereafter, as shown in
FIG. 28
, an impurity of the same conductivity type as source and drain regions
111
a
and
111
b
are introduced by ion implantation into selective silicon films
112
a
and
112
b
, and by heat treatment, the selective silicon films
112
a
and
112
b
are adapted to have lower resistance, whereby low resistance selective silicon films
113
a
and
113
b
are formed, respectively.
In this manner, an MOS transistor T including a polysilicon gate
107
, a pair of source and drain regions
111
a
and
111
b
and low resistance selective silicon films
113
a
and
113
b
are formed.
Thereafter, referring to
FIG. 29
, an interlayer silicon oxide film
114
is formed by the CVD method on silicon substrate
101
to cover the MOS transistor T. On the interlayer silicon oxide film
114
, a prescribed photoresist pattern (not shown) is formed. Using the photoresist pattern as a mask, the interlayer silicon oxide film
114
is anisotropically etched, whereby contact holes
121
a
and
121
b
exposing surfaces of low resistance selective silicon films
113
a
and
113
b
are formed, respectively.
Thereafter, a prescribed metal film is formed by sputtering, for example, and a prescribed heat treatment is performed. Thus, a titanium silicide film
115
, a titanium nitride film
116
and a tungsten film
117
are formed in contact holes
121
a
and
121
b
. Thereafter, on the interlayer silicon oxide film
114
, a prescribed metal interconnection (not shown) electrically connected to tungsten film
117
is formed. An interlayer insulating film and a passivation film (both not shown), for example, are further formed on interlayer silicon oxide film
114
, to cover the metal interconnection. By prescribed photolithography and etching, interconnection pads and the like are formed.
The conventional semiconductor device is thus completed through the above described steps.
As described above, in the conventional semiconductor device, the sidewall oxide film
109
a
of silicon oxide film has been applied as a sidewall insulating film. Here, in the step of
FIG. 27
, when selective silicon films
112
a
and
112
b
are formed, selectivity of silicon epitaxial growth is established on the source and drain regions
111
a
and
111
b
(silicon substrate) and on the sidewall oxide film
109
a
(silicon oxide film) adjacent thereto, and therefore it is possible to form selective silicon films
112
a
and
112
b
selectively only on the source and drain regions
111
a
and
111
b.
There has been a demand to increase degree of integration of the semiconductor devices for miniaturization. In order to meet such a demand, use of a silicon nitride film in place of the conventional silicon oxide film as the sidewall insulating film is expected. This is to ensure registration margin for photolithography when contact holes
121
a
and
121
b
are to be formed in interlayer silicon oxide film
114
.
Use of the silicon nitride film as the sidewall insulating film may lead to the following problem. The silicon nitride film has lower selectivity with respect to the silicon substrate at the time of silicon epitaxial growth, as compared with the silicon oxide film. Therefore, in the process of epitaxial growth of the selective silicon film having the prescribed film thickness, silicon island
118
would be formed on the surface of sidewall insulating film
130
of silicon nitride film, as shown in FIG.
30
.
If such silicon islands
118
are formed, the selective silicon film
112
b
would be electrically connected to other selective silicon film through the silicon island
118
, possibly causing electric short-circuit of source and drain region
111
b
with other source and drain regions. As a result, the semiconductor device cannot perform a desired operation.
SUMMARY OF THE INVENTION
The present invention was made to solve the above described problem. One object of the present invention is to provide a semiconductor device capable of ensuring electrical insulation and another object is to provide a method of manufacturing such a semiconductor device.
According to an aspect, the present invention provides a semiconductor device including a semiconductor substrate having a main surface, first and second conductive layers, a silicon nitride film and a protective layer. The first and second conductive layers are formed spaced from each other on the main surface of the semiconductor substrate. The silicon nitride film is formed on the main surface of the semiconductor substrate traversing between the first and second conductive layers. The protective layer is formed on the surface of the silicon nitride film and at least until the first and second conductive layers are formed to a prescribed film thickness, prevents deposition of the material of the first and second conductive layers on the surface of the silicon nitride film.
In this structure, deposition of the material of the first and second conductive layers on the silicon nitride film can be prevented by the protective film until the first and second conductive layers are formed to a prescribed film thickness. As a result, electrical short-circuit between the first and second conductive layers through the material can be prevented.
Especially when the semiconductor substrate includes a silicon substrate and the first and second conductive layers include silicon epitaxial growth layer, the protective layer should preferably be a layer preventing the material of the epitaxial growth layer. Here, it is possible to prevent deposition of silicon pieces on the surfaces of the silicon nitride film. Preferably, the semiconductor device includes a pair of impurity regions of a prescribed conductivity type formed spaced from each other on the main surface of the semiconductor substrate, an electrode portion formed on the main surface of the semiconductor substrate sandwiched between the pair of impurity regions, and sidewall insulating films formed on the side surfaces of the electrode portion, in which the first and second conductive
Furukawa Taisuke
Maruno Shigemitsu
Miura Naruhisa
Nakahata Takumi
Oishi Toshiyuki
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Thompson Craig
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