Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-08
2003-02-11
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06518627
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and, more particularly, to a semiconductor device including a resistive element and a method of manufacturing the same.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory) is a well known type of semiconductor device. A DRAM includes a resistive element for generating a predetermined voltage to various parts inside the device. This resistive element is connected between a source potential VDD and a ground potential GND, and a voltage therebetween is divided by the resistive element to generate a necessary voltage. The resistive element has high resistance to restrict the electric power to be consumed. For example, the resistive element is formed of a polycrystalline silicon film, and formed at the same time a plate electrode of a capacitive element included in the DRAM is formed.
FIGS. 7
to
10
illustrate a DRAM including a resistive element.
FIG. 7
is a plan view showing the structure of the DRAM.
FIG. 8
is a cross sectional view taken along a line C—C of FIG.
7
.
FIG. 9
is a diagram showing an equivalent circuit of the DRAM.
FIG. 10
is a cross sectional view showing the structure of the DRAM.
As illustrated in
FIGS. 7 and 8
, the DRAM includes a resistive element
54
in a resistive element formation area on a P-type silicon substrate
51
. The resistive element
54
is formed of polycrystalline silicon, and is formed while forming a plate electrode (upper electrode) of a capacitive element
60
(to be described later) included in a DRAM.
One end of the resistive element
54
is connected to a source potential VDD, and the other end thereof is connected to a ground potential GND. An intermediate terminal
55
for outputting an intermediate potential HVDD is formed at one point of the resistive element
54
.
As shown in
FIG. 10
, the capacitive element
60
is formed in a transistor formation area of the P-type silicon substrate
51
on which the resistive element
54
is also formed.
The capacitive element
60
includes a storage electrode (lower electrode)
65
formed in a contact hole
68
formed in a first interlayer insulating film
52
, a capacitive insulating film
66
, and a plate electrode (upper electrode)
67
which is formed of a polycrystalline silicon film and formed on the capacitive insulating film
66
. P
+
-type well area
61
is formed in the P-type silicon substrate
51
. N
+
-type areas
62
and
63
are formed in the P
+
-type well area
61
.
In such a DRAM, as illustrated in
FIG. 9
, a parasitic capacity C is formed from the resistive element
54
, wiring
57
formed adjacent to the resistive element
54
, and the interlayer insulating film
56
. The intermediate potential HVDD is output from the intermediate terminal
55
. The intermediate potential HVDD is obtained by dividing a voltage between the source potential VDD and the ground potential GND by the first resistance R
1
and the second resistance R
2
of the resistive element
54
.
In the DRAM, the resistive element
54
is formed while forming the plate electrode of the capacitive element
60
. The resistive element
54
has the resistance substantially with the same accuracy as that of the plate electrode
67
of the capacitive element
60
, thus causing the following problems.
First, the accuracy of the resistance of the resistive element
54
is low, therefore, it is difficult to generate a predetermined voltage with high accuracy. More specifically, the plate electrode
67
is formed to have resistivity with not high level of accuracy, resulting in a large variation in the resistivity. This causes a large variation in the resistivity of the resistive element
54
formed while the plate electrode
67
is formed. The resistive element
54
having resistivity with low accuracy, thus it is difficult to generate a predetermined voltage accurately.
Second, the resistive element
54
is small in size and is formed of a layer having high resistivity. Thus, the potential of the resistive element
54
may largely vary on an influence of a couple noise, resulting in inappropriate operations of the semiconductor device.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a semiconductor device, including a resistive element which is not influenced by a noise from wiring, and a method of manufacturing the same.
Another object of the present invention is to provide a semiconductor device including a resistive element having resistivity with high accuracy.
In order to achieve the above objects, there is provided a method of manufacturing a semiconductor device, the method comprising:
forming an insulating film on a substrate having a resistive element formation area and a transistor formation area;
forming a conductive layer on the insulating film;
patterning the conductive layer, thereby to form a resistive element in the resistive element formation area and a gate electrode in the transistor formation area, respectively;
doping an impurity in the substrate while using the resistive element and the gate electrode as masks to form a doped layer in the resistive element formation area, and a source area and a drain area in the transistor formation area;
forming an interlayer insulating film on the resistive element and the gate electrode; and
forming wiring on the interlayer insulating film.
REFERENCES:
patent: 5371701 (1994-12-01), Lee et al.
patent: 5463236 (1995-10-01), Sakao
patent: 5801079 (1998-09-01), Takaishi
patent: 5804851 (1998-09-01), Noguchi et al.
Elms Richard
Menz Douglas
Young & Thompson
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