Hardmask gate patterning technique for all transistors using...

Details Hardmask gate patterning technique for all transistors using... Hardmask gate patterning technique for all transistors using...

2002-01-09

2003-12-16

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S947000, C438S950000

Reexamination Certificate

active

06664173

ABSTRACT:

TECHNICAL FIELD
This invention relates to semiconductor processing and semiconductor elements.
BACKGROUND
In the production of semiconductor devices, particularly MOS or CMOS devices, a layer of gate material such as polysilicon typically is etched to form a transistor gate structure. As one aspect of forming the gate, the length of the gate, called the “critical dimension” or “CD,” should be closely controlled. Often, it is desirable to use a “minimum-size” device with the smallest achievable critical dimension. With photolithography, the size of the critical dimension is limited by, among other factors, the wavelength of the light used. As the size of the critical dimension becomes smaller, for example below 100 nanometers or below 50 nanometers, the limits of conventional photolithography are being reached.
A minimum-size device may be produced using a spacer gate technique that uses conventional photolithography to create a structure with a sidewall on top of the gate material. A film of hardmask material, such as silicon dioxide or silicon nitride, is deposited with a certain thickness on top of the gate material and etched to create a spacer. The spacer has a width that is approximately the thickness of the hardmask film. The spacer is used to form the desired minimum-size transistor gate structure, which has a critical dimension of approximately the spacer width.
The spacer gate technique can raise delamination issues when the gate material adjacent to the spacer is etched. In particular, after the gate material is etched away, the remaining stack of gate material and hardmask spacer may have a large aspect ratio (the ratio of the height to the width of the structure). A large aspect ratio, for example a ratio of 6:1 or higher, can lead to delamination of the hardmask layer, which may result in a lower yield.
It may also be desirable to use a device having a larger critical dimension than the minimum-size device. A device having a critical dimension that is the next size larger than a minimum-size device may be called a “next-to-minimum size” device. Devices with critical dimensions larger than the minimum-size device may be created using conventional photolithography or other known techniques.
When a mix of more than one size device is needed, a spacer gate technique may be used to define minimum-size devices and classical photolithography techniques may be used to define all other gate sizes, including next-to-minimum size devices. Typically, the processing may be optimized for a spacer gate technique or classical photolithography, but it may be difficult to optimize the processing for both.
While the spacer gate technique tends to provide good critical dimension control, the associated photoresist process may not provide adequate critical dimension control. This may result in the minimum size devices having good critical dimension control but all other sizes having undesirable variations in critical dimension.


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J. Horstmann et al., “Characterisation of Sub-100 nm-MOS-Transistors Processed by Optical Lithography and a Sidewall-Etchback Technique”, Microelectronic Engineering vol. 30 1996, pp. 431-434.
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