Frequency detection circuit for clock recovery

Details Frequency detection circuit for clock recovery Frequency detection circuit for clock recovery

1999-02-23

2003-11-04

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C331S011000, C331S010000, C331S017000, C345S180000

Reexamination Certificate

active

06643346

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a frequency detection circuit for use with digital communication systems. More particularly, the present invention relates to a frequency detection circuit that provides a reliable frequency difference signal that may be utilized in extracting an underlying input clock signal. An exemplary application for the present invention is a clock recovery circuit that employs a phase locked loop.
BACKGROUND OF THE INVENTION
Clock signals are routinely utilized during the transmission of digital data. Clock signals associated with the data are required for regenerating and demultiplexing the data stream, i.e., the clock is required to convert the continuous-time received signal into a discrete-time sequence of data symbols. After conversion to a sequence of data symbols, a decision can be made as to whether a given signal is a “1” or a “0”. Although many digital systems existing today transmit a clock signal separate from a data stream, for digital communication systems, the transmission of a separate clock is inefficient and cumbersome, since it typically requires several additional components, bandwidth and power.
Accordingly, for digital communication systems, it is more appropriate to extract the clock signal directly from the input data stream rather than to transmit the clock signal separately. However, the underlying recovered clock signal has typically been attenuated and degraded by noise and other imperfections in the modulation and transmission process, and therefore should be reconstructed before further processing. This reconstruction process may include the amplification and filtering of the signal, followed by a sampling of the signal at a time in which there is a low probability of error, i.e., the time of sampling in which a decision can be made as to whether a given digital signal is a “1” or a “0”.
In accordance with one high speed digital communication technique, the digital data is transmitted as a series of bits, with each bit occurring within its own time slot. Generally, the occurrence of these time slots is periodic with the underlying clock signal. Two common forms of Pulse Amplitude Modulation (PAM) for the digital signals (Return to Zero (RZ) and Non-Return to Zero (NRZ) modulation) are shown in
FIGS. 7A and 7B
. With reference to
FIG. 7A
, RZ modulation is configured such that a “1” is generated by the signal going “high” for a part of the bit period and then returning to the “0” level during the remaining bit period, while a “0” is generated by the signal remaining low during the entire bit period. For NRZ modulation, the signal will typically remain a “1” or a “0” for the entire bit slot. With reference to
FIG. 7B
, the spectra of both RZ and NRZ signals as modulated by random data are shown. Although the RZ clock signal, unlike the NRZ signal, contains a component at the clock frequency, i.e., a value at 1/T, 2/T and 3/T which can be used for frequency control, the RZ signal utilizes significantly more bandwidth than the NRZ signal. With the emergence of the Synchronous Optical Network (SONET) OC-N standards, it is preferable to extract the clock signal from the input of a NRZ data stream, partly due to the reduced bandwidth requirements of NRZ signals.
Once an input of a NRZ data stream is received, and a regenerated signal having various distortions as described above is produced, the corresponding clock signal is extracted. Two methods are commonly used to extract the clock signal. The first method is to apply a very high-Q filter, such as a Surface Acoustic Wave filter, which typically builds up a component at the clock frequency and then filters out the missing transitions in the conditioned data. However, unless the filtered signal includes substantially the same clock signal as that underlying the input data, phase errors will accumulate. Accordingly, if, for example, the extracted clock signal is as little as 1 hertz different than the underlying clock signal, the decision period for determining whether a “1” or a “0” will be improperly located, and thus the digital communication system will not properly function.
Another method for extraction is to use a phase locked loop (PLL) to lock an oscillator onto the input data stream. With reference to
FIG. 1
, a clock extraction circuit
100
utilizing a PLL
120
is shown. Reconfigured input data comprising Pseudo-Return-to-Zero data (PRZ), i.e., a modified version of the input data stream; may be received by PLL
120
. Further, PRZ data may be produced within a non-linear clock extractor
110
before transmission to PLL
120
. However, for some phase detectors, such as, for example, a Hogge phase detector, non-linear clock extractor
110
is not typically used. PLL
120
generally comprises a phase detector
140
suitably connected to a loop filter
150
which in turn is coupled to a voltage-controlled oscillator (VCO)
160
. Phase detector
140
is configured to measure the phase error between the input y(t) and the VCO output v(t). The resulting error signal e(t) can be filtered through loop filter
150
to become a control signal c(t) that drives VCO
160
. Loop filter
150
is typically configured with a narrow bandwidth that is designed to minimize output phase jitter due to external noise. If the phase of VCO
160
is ahead of the phase of the input signal y(t), the control signal c(t) may be suitably reduced. If on the other hand the phase of VCO
160
gets behind the phase of the input signal y(t), the control signal c(t) may be suitably increased. Accordingly, PLL
120
is designed to drive the error signal e(t) to essentially zero, as dictated by the bandwidth of the loop filter
150
, and thus allow VCO
160
to track the phase of the input signal to produce a recovered clock signal.
Once PLL
120
is “locked” onto the clock signal of the input data stream, the clock signal is applied to a decision circuit
130
, which also looks at the input data stream, i.e., the NRZ data stream. Decision circuit
130
generally includes a comparator or gain stage and then a sampling stage for sampling the data. Accordingly, decision circuit
130
samples the input data stream and, utilizing the recovered clock signal, correspondingly outputs a “1” or a “0” depending on the value of the incoming data stream during the sampling period. Further, a fixed or manually adjustable relative phase delay is often included to align the clock and data signals when in “lock” at decision circuit
130
.
As the input data stream is received, variations and other corruptions within the input data stream are present as described above. To quantify the amount of signal degradation, and to check the performance of clock extraction circuit
100
, an eye diagram may be utilized. With reference to
FIG. 5
, an eye diagram
500
(which may be generated by an oscilloscope) provides many overlaid traces of small sections of the input data stream and visually summarizes the variations and corruptions of the input data stream. Within eye diagram
500
, a decision window
510
is formed which provides the optimum time for sampling the input data signal. Other characteristics include an amplitude margin
520
and a phase margin
530
. Amplitude margin
520
, i.e., the vertical eye opening, generally indicates the immunity to noise for the decision circuit while phase margin
530
, i.e., the horizontal eye opening, generally indicates the immunity to errors in the timing phase. Although, the beneficial effect on increasing the loop bandwidth is to increase the horizontal eye opening, and thus the immunity to phase errors, the increased bandwidth can introduce more noise into the decision circuit. Thus, in designing digital communication systems, there is a basic system tradeoff between excess bandwidth, noise immunity and the complexity of the timing recovery circuit.
Due to the narrow bandwidth typically required, a problem encountered by the use of PLL
120
for clock recovery is the limited lock acquisition range. For example, if an input data stream is designed to provide

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