Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-09-28
2003-10-28
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S153000
Reexamination Certificate
active
06638798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device of high-voltage CMOS structure, and a method of fabricating such a semiconductor device of high-voltage CMOS structure.
2. Description of the Related Art
Heretofore, semiconductor devices of CMOS (Complementary Metal Oxide Semiconductor) structure comprising a pair of P- and N-type MOS transistors formed on a single SOI (Silicon-On-Insulator) substrate have been used in various applications. Such semiconductor devices of CMOS structure are available in a variety of types. CMOS circuits for use as plasma display panel drive circuits need to withstand to high voltages. It has been proposed to employ an offset structure for P- and N-type MOS transistors in such CMOS circuits.
One conventional semiconductor device of CMOS structure will be described below with reference to FIGS.
1
through
5
(
b
) of the accompanying drawings.
FIG. 1
is a fragmentary vertical cross-sectional view showing a multilayer structure of a CMOS circuit as the conventional semiconductor device, and FIGS.
2
(
a
) through
5
(
b
) are fragmentary vertical cross-sectional views illustrative of successive steps of a process of fabricating the CMOS circuit shown in FIG.
1
.
The conventional semiconductor device will be described on the assumption that layers are successively formed on a substrate in an upward direction. Such a direction is employed by way of example only for the sake of brevity, and will not limit any direction in which the semiconductor device is actually fabricated and used. Layers or films with a higher concentration are indicated by P
+
and N
+
, and those with a lower concentration are indicated by P
−
and N
−
. In FIGS.
1
through
5
(
b
) and other figures, “P+”, “N+”, “P−”, “N−” should be construed to mean “P
+
”, “N
+
”, “P
−
”, “N
−
”, respectively.
As shown in
FIG. 1
, a CMOS circuit
1
has a single SOI substrate
2
of a P-type which is a first conductivity type. On the SOI substrate
2
, there are disposed a P-channel first transistor
3
of the first conductivity type and an N-channel second transistor
4
of a second conductivity type. Each of the first and second transistors
3
,
4
is of an offset LMOS (Lateral MOS) structure.
The SOI substrate
2
comprises first and second substrates
5
,
6
each of the P
−
-type which is the first conductivity type. The first and second substrates
5
,
6
are integrally joined to each other by an embedded oxide film
7
. The first and second transistors
3
,
4
are disposed in only the first substrate
5
that is positioned above the embedded oxide film
7
. The first and second transistors
3
,
4
are isolated from each other by a trench
8
and a laminated oxide film
9
.
The P-channel first transistor
3
comprises a source
11
, a gate
12
positioned inside of the source
11
, and a drain
13
positioned centrally therein. The source
11
, the gate
12
, and the drain
13
are positioned on a single N
−
-type well
14
disposed in the first substrate
5
.
The source
11
of the first transistor
3
comprises a P-type source diffusion layer
21
positioned on the N
−
-type well
14
, a P
+
-type source contact diffusion layer
22
positioned on an upper surface of the P-type source diffusion layer
21
, and an N
+
-type back-gate contact diffusion layer
23
positioned on the N
31
-type well
14
outside of the P
+
-type source contact diffusion layer
22
. A source electrode
24
is positioned on the contact diffusion layers
22
,
23
.
The drain
13
of the first transistor
3
comprises a P-type drain offset diffusion layer
25
positioned on the N
−
-type well
14
and a P
+
-type drain contact diffusion layer
26
positioned centrally on an upper surface of the P-type drain offset diffusion layer
25
. A drain electrode
27
is positioned on the P
+
-type drain contact diffusion layer
26
.
The drain offset diffusion layer
25
and the source diffusion layer
21
project from the respective contact diffusion layers
26
,
22
toward the gate
12
, and a field oxide film
28
is positioned on upper surfaces of the offset regions of the drain offset diffusion layer
25
and the source diffusion layer
21
. A gate electrode
29
is positioned on an upper surface of the field oxide film
28
which doubles as a gate oxide film, and a gate extension electrode
30
is positioned on an upper surface of the gate electrode
29
.
The N-channel second transistor
4
is disposed in juxtaposed relation to the P-channel first transistor
3
. The N-channel second transistor
4
has a source
41
, a gate
42
positioned inside of the source
41
, and a drain
43
positioned centrally therein.
In the source
41
of the second transistor
4
, the P
−
-type first substrate
5
serves as a source base layer
50
, and a P-type source shield diffusion layer
51
is positioned on the source base layer
50
. An N
+
-type source contact diffusion layer
52
and a P
+
-type back-gate contact diffusion layer
53
are positioned respectively on inner and outer regions of an upper surface of the source shield diffusion layer
51
. A source electrode
54
is positioned on the contact diffusion layers
52
,
53
.
In the drain
43
of the second transistor
4
, an N-type drain offset diffusion layer
55
is disposed in the P
−
-type first substrate
5
. An N
+
-type drain contact diffusion layer
56
is positioned centrally on an upper surface of the offset diffusion layer
55
. A drain electrode
57
is positioned on the drain contact diffusion layer
56
.
The drain offset diffusion layer
55
and the source shield diffusion layer
51
project from the respective contact diffusion layers
56
,
52
toward the gate
42
, and a field oxide film
58
and a gate oxide film
59
are positioned on upper surfaces of the offset regions of the drain offset diffusion layer
55
and the source shield diffusion layer
51
. A gate electrode
60
is positioned on an upper surface of the oxide films
58
,
59
, and a gate extension electrode
61
is positioned on an upper surface of the gate electrode
60
.
The electrodes
24
,
27
,
30
,
54
,
57
,
61
of the first and second transistors
3
,
4
extend through the laminated oxide film
9
on which an isolation layer (not shown) is positioned. The isolation layer is partly removed to expose the electrodes
24
,
27
,
30
,
54
,
57
,
61
, which provide connection pads (not shown).
In the CMOS circuit
1
of the above structure, since both the P-channel first transistor
3
and the N-channel second transistor
4
are of an LMOS structure, currents flow laterally from the source electrodes
24
,
54
through the gates
12
,
42
to the drain electrodes
27
,
57
.
Furthermore, both the transistors
3
,
4
are of an offset structure in which the drain offset diffusion layers
25
,
55
extend to lower surfaces of the field oxide film
28
and the field and gate oxide films
58
,
59
. Therefore, the breakdown voltage of these transistors
3
,
4
is so high that the transistors
3
,
4
is capable of switching high voltages.
A process of fabricating the CMOS circuit
1
will briefly be described below with reference to FIGS.
2
(
a
) through
5
(
b
).
As shown in FIG.
2
(
a
), first and second substrates
5
,
6
of P
−
-type silicon are prepared, and integrally joined to each other by an embedded oxide film
7
in the form of an SIO
2
film having a thickness of about 2 &mgr;m. The first substrate
5
is ground to a thickness of about 5 &mgr;m, thus producing a single SOI substrate
2
.
Then, as shown in FIG.
2
(
b
), a thermal oxide film (not shown) is formed on the entire upper surface of the first substrate
5
, and patterned into a mask
71
of predetermined shape. An impurity of phosphorus is introduced into the first substrate
5
through openings of the mask
71
by ion implantation. The assembly is heated to diffuse the introduced phosphorus d
NEC Electronics Corporation
Pham Long
LandOfFree
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