Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-09
2003-02-18
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S309000
Reexamination Certificate
active
06521937
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device providing substantial capacitance in memory cells and a method for preparing the semiconductor device.
2. Discussion of Background
In
FIG. 11
is shown a cross-sectional view of the structure of a conventional semiconductor device. In this Figure, reference numeral
1
designates a semiconductor substrate, reference numeral
2
designates a gate lines formed on the semiconductor substrate
1
, reference numeral
3
designates diffused regions in the semiconductor substrate
1
, reference numeral
4
designates one of bit lines connected to diffused regions, reference numeral
5
designates an interlayer dielectric film covering the bit lines
4
, and reference numeral
6
designates contact holes in the interlayer dielectric film
5
extending to the diffused regions
3
.
Reference numeral
7
designates storage nodes, which fill the contact holes
6
and provided on the interlayer dielectric film
5
. Reference numeral
8
designates insulating films, which are cover the storage nodes
7
. Reference numeral
9
designates a cell plate, which covers the insulating films
8
. The storage nodes
7
, the insulating films
8
and the cell plate
9
form a capacitor
10
. Such a capacitor is provided at plural locations in a single layer.
The conventional semiconductor device thus constructed has difficulty in ensuring required capacitance since the distance between the storage nodes of the respective capacitors decreases and the storage nodes per se have areas that decrease as the semiconductor device becomes smaller.
In order to solve this problem, there is a method to extend the height of the storage nodes per se to enlarge the area, increasing the capacitance. In this case, there has been created a problem in that large steps are provided between regions with the storage nodes and regions without the storage nodes and that cause problems in subsequent processing.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve these problems, and to provide a semiconductor device capable of ensuring much capacitor capacity and a method for preparing the semiconductor device.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a plurality of memory cells, and the respective memory cells having capacitors, the capacitors of adjoining memory cells provided in different layers, wherein a region with a capacitor formed therein and a region with an adjoining formed therein partly overlap in a planar direction.
According to a second aspect of the present invention, the capacitors are alternately provided in an upper layer and a lower layer in the first aspect.
According to a third aspect of the present invention, the respective capacitors have storage nodes formed in a cylindrical shape and/or formed so as to have a rough surface in the first or second aspect.
According to a fourth aspect of the present invention, the respective capacitors have at least of an upper side and a lower side of storage nodes provided with a cell plate in one of the first to third aspects.
According to a fifth aspect of the present invention, there is provided a method for preparing a semiconductor device comprising the steps of forming holes in an interlayer dielectric film provided on a semiconductor substrate up to a semiconductor substrate to form a plurality of capacitors at certain intervals for electrical conduction with a semiconductor substrate in a lower layer on the interlayer dielectric film; and forming holes up to the semiconductor substrate at certain spaced locations to form a plurality of capacitors for electrical conduction with the semiconductor substrate in an upper layer above the lower layer so as to partly overlap regions in the lower layer with the capacitors formed therein and regions in the upper layer with the capacitors formed therein in a planar direction.
As explained, in, accordance with the first aspect, the semiconductor device with the plural memory cells have the capacitors of adjoining memory cells provided in different layers, wherein a region with a capacitor formed therein and a region with an adjoining capacitor formed therein partly overlap in a planar direction. As a result, the semiconductor device can be provided so as to have the capacitor area enlarged and consequently to ensure much capacitor capacity.
In accordance with the second aspect, the capacitors are alternately provided in the upper layer and the lower layer in the first aspect. As a result, the semiconductor device can be provided to be formed easily.
In accordance with the third aspect, the respective capacitors have storage nodes formed in a cylindrical shape and/or formed so as to have a rough surface in the first or second aspect. As a result, the semiconductor device can be provided so as to have the capacitor area further enlarged and consequently to ensure much more capacitor capacity.
In accordance with the fourth aspect, the respective capacitors have at least one of an upper side and a lower side of storage nodes provided with a cell plate in any one of the first to third aspects. As a result, the semiconductor device can be provided so as to have the capacitor area further enlarged and consequently to ensure much more capacitor capacity.
In accordance with the fifth aspect, there is provided the method for preparing a semiconductor device comprising the steps of forming holes in the interlayer dielectric film provided on the semiconductor substrate up to the semiconductor substrate to form a plurality of capacitors at certain intervals for electrical conduction with a semiconductor substrate in a lower layer on the interlayer dielectric film; and forming holes up to the semiconductor substrate at certain spaced locations to form a plurality of capacitors for electrical conduction with the semiconductor substrate in an upper layer above the lower layer so as to partly overlap regions in the lower layer with the capacitors formed therein and regions in the upper layer with the capacitors formed therein in a planar direction.
REFERENCES:
patent: 5135883 (1992-08-01), Bae et al.
patent: 5138412 (1992-08-01), Hieda et al.
patent: 5362665 (1994-11-01), Lu
patent: 5541428 (1996-07-01), Nagatomo
patent: 5731949 (1998-03-01), Ko
patent: 6274427 (2001-08-01), Iwasaki
patent: 2-94471 (1990-04-01), None
patent: 4-257257 (1992-09-01), None
patent: 4-297065 (1992-10-01), None
patent: 7-22595 (1995-01-01), None
patent: 10-256508 (1998-09-01), None
patent: 91-19225 (1991-11-01), None
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