Semiconductor memory device and bit line isolation gate...

Details Semiconductor memory device and bit line isolation gate... Semiconductor memory device and bit line isolation gate...

2001-09-07

2003-02-18

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S203000

Reexamination Certificate

active

06522597

ABSTRACT:

BACKGROUND OF THE INVENTION
Korean Application Number 2000-56248 filed Sep. 25, 2000, entitled “Semiconductor memory device and bit line isolation gate arrangement method thereof,” is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to isolation gate arrangement in semiconductor memory devices, and more particularly, to a bit line isolation gate arrangement for reducing bit line precharge time.
2. Background of the Invention
In conventional high-density semiconductor memory devices, such as dynamic random access memories (DRAMs), in order to reduce power consumption, a memory cell array is often partitioned into multiple memory cell array blocks, wherein each memory cell array block can be selectively enabled. Typically, the memory cell array blocks remain in an inactive, low-power state until access to an individual cell is desired.
To access a cell, only the associated memory cell array block is activated via control lines. Typically, these control lines include block, row, and column addressing lines. The operational control sequencing needed to transfer data in and out of the addressed cell is accomplished using a pair of conductor lines arranged as “bit line pairs.” A first bit line pair controls an input stage of the memory cell, and a second bit line pair controls an output stage of that cell. These bit line pairs are further connectively coupled to the multiple memory cell array blocks throughout the array. By selectively activating the line pairs, data transfers can be made between the memory cell and an external data bus.
A significant disadvantage of such an arrangement is that in the fabrication of the device, regional anomalies in the device are produced due to process variations. This can be manifested as differences in contact resistance from one side of an integrated circuit to the other. Coupled with intrinsic capacitances associated with integrated components making up the device, a node having higher contact resistance will be characterized by a longer charge time than a node having a lower contact resistance. This variation in the speed of state transitions significantly degrades the performance of the DRAM.
Accordingly, “precharge” lines are connected to nodes where additional charge would be required to speed up voltage transitions associated with such data bit state changes in each memory cell array block. In conventional configurations, portions of these memory cell array block pre-charge lines are connected to internal semiconductor components of the memory cell array block, and other portions are connected to input/output (I/O) buffering components located at block boundaries of the memory cell array block. Since these buffering components of each memory cell array block are each connected to a universal external I/O buffer in the DRAM device, the I/O buffer portions of the precharge lines are in turn universally connected to the I/O buffering components of the other memory cell array blocks in the DRAM device. Thus, I/O buffering devices on these “shared” lines are subjected to a collective pre-charge that is significantly greater than the pre-charge available to device nodes that are internal to the memory cell array block boundaries and which are connected to only a single pre-charge line. This causes mismatches in the transition times of the semiconductor devices located within an internal memory cell array block “chain” as compared to the I/O component regions, again with attendant degradation of the DRAM device. There is an obvious need for an improved structure that will provide for more uniform transition times and less dependency on contact resistance of the devices.
SUMMARY OF THE INVENTION
In a preferred embodiment of the present invention, state change transition times of a semiconductor memory device are reduced by reducing contact resistance associated with unshared input/output (I/O) lines. To minimize the difference in transition times between shared I/O lines having dual precharge circuits and non-shared I/O lines which have only a single precharge circuit, effective contact resistance of the non-shared I/O lines are reduced through the elimination of unnecessary isolation gates with their attendant impedances. This provides faster transition times for the non-shared I/O lines.
As claimed in a feature of an embodiment of the present invention, there is provided an integrated semiconductor memory device comprising a plurality of memory cell array blocks, each memory cell array block having an input port and an output port and further comprising a plurality of memory cells, an input amplifying means for amplifying a received data signal, an output amplifying means for amplifying a stored data signal, a first precharging means which is electrically associated with the input port, and a second precharging means which is electrically associated with the output port, a first plurality of differential conductor pairs, each pair of conductor pairs being associated with a single data bit and being electrically associated with an input port of one of the plurality of memory cell array blocks, a second plurality of differential conductor pairs, each pair being associated with a single data bit and each pair being electrically associated with an output port of one of the plurality of memory cell array blocks, a plurality of isolation components, each one switchably isolating an input port of a first memory cell array block from an output port of a second memory cell array block when the two memory cell array blocks are electrically coupled; and characterized in that the two ports are further isolated from an associated differential conductor pair, and an address decoding means for selectively enabling a memory cell array block in the plurality of memory cell array blocks in response to a unique address signal, wherein at least two of the plurality of memory cell array blocks, which are not connectively coupled to an adjacent memory cell array block, have a port that is directly connected to an input/output conductor.
As claimed in another feature of an embodiment of the present invention, the first precharging means comprises a switchable energy source that is electrically associated with each one of the input ports of the memory cell array block. The first precharging means may provide a predetermined quantity of charge to a plurality of intrinsic capacitances that are associated with the respective ports in order to increase the speed of voltage transitions at the ports. The second precharging means may comprise a switchable energy source that is electrically associated with each one of the input ports of the memory cell array block. The second precharging means may also provide a predetermined quantity of charge to a plurality of intrinsic capacitances that are associated with the respective ports in order to increase the speed of voltage transitions at the ports.
As claimed in another feature of an embodiment of the present invention, there is provided an integrated semiconductor memory device comprising a first memory cell array block having a plurality of control lines and a first pair of conductors that directly and electrically connect the first memory cell array block to a first node, a first precharging circuit electrically connected to the first pair of conductors, a second pair of conductors that electrically connect the first memory cell array block to a second node using a first isolation component, a second precharging circuit electrically connected to the second pair of conductors, a second memory cell array block that is electrically connected to the second node using a second isolation component, and a third precharging circuit electrically connecting the second memory cell array block to the second isolation component. A first sense amplifier may be operationally coupled to the first node, and a second sense amplifier may be operationally connected to the second node. The first conductor pair may be operated without an isolation circuit being placed between the first nod

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