Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-17
2003-02-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000
Reexamination Certificate
active
06515331
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, to metal-oxide-semiconductor field effect transistors (MOSFET) devices for use in electrostatic discharge (ESD) protection devices and methods for their manufacture.
2. Description of the Related Art
Electrostatic discharge (ESD) protection devices are commonly employed in an integrated circuit (IC) to protect electronic devices in the IC from spurious pulses of excessive voltage (namely, an “ESD event”). See, for example, S. M. Sze,
VLSI Technology, Second Edition
, 648-650 (McGraw Hill, 1988). A variety of conventional ESD protection devices that make extensive use of diodes, metal-oxide-semiconductor field effect transistors (MOSFETs) and bipolar transistors are known in the field.
Referring to
FIG. 1
, a representative conventional MOSFET structure
10
for use in an ESD protection device is illustrated. The MOSFET structure
10
includes a gate silicon dioxide layer
12
overlying P-type silicon substrate
14
. Also present in the P-type silicon substrate
14
are N-type source region
16
and N-type drain region
18
. N-type Lightly-Doped-Drain (LDD) source extension region
20
and N-type LDD drain extension region
22
are disposed in the P-type silicon substrate
14
underneath gate silicon dioxide layer
12
and adjacent to the N-type source region
16
and N-type drain region
18
, respectively. In addition, channel region
24
is located in the P-type silicon substrate
14
and connects the N-type LDD source extension region
20
to the N-type LDD drain extension region
22
underneath the gate silicon dioxide layer
12
. A patterned polysilicon gate layer
28
overlies gate silicon dioxide layer
12
. Gate sidewall spacer
26
, typically of silicon dioxide or silicon nitride, is formed on the edges of the patterned polysilicon gate layer
28
and gate silicon dioxide layer
12
.
Conventional MOSFET structures are designed to exhibit breakdown characteristics only at voltages well above their standard operating supply voltage. However, during an ESD event, MOSFET structures used in ESD protection devices exhibit significant current conduction via a parasitic lateral bipolar mechanism. For a further description of such current conduction in MOSFET structures via a parasitic lateral bipolar mechanism, see sections 3.5.2 and 4.2.3 of Ajith Amerasekera and Charvaka Duvvury,
ESD in Silicon Integrated Circuits
, 47-49, 69-72 (John Wiley & Sons 1995), which are hereby fully incorporated by reference.
FIG. 2
is a graph illustrating the typical current versus voltage characteristics (using arbitrary axes) of a conventional grounded-gate NMOSFET structure for use in an ESD protection device. An electrical schematic illustrating the conventional NMOSFET structure
10
of
FIG. 1
in a grounded-gate configuration is provided in FIG.
3
. The current versus voltage characteristics of
FIG. 2
are representative of a 50 micron wide grounded-gate NMOSFET structure operating in the voltage range of 0 to 10 volts and the current range of 0 amp to 1 amp. In Region
1
, the grounded-gate NMOSFET structure behaves as a standard MOS transistor device with a relatively low level of leakage current. In Region
2
, the grounded-gate NMOSFET is in the operating regime known as the first breakdown region. Region
3
represents the operating regime, where the N-type source region of the grounded-gate NMOSFET structure is being forward biased, thereby initiating current conduction through a parasitic lateral bipolar mechanism.
The transition point between Region
2
and Region
3
is the “first breakdown” point, where the grounded-gate NMOSFET structure triggers into “snap-back.” The transition point is characterized by its trigger voltage (V
t1
) and trigger current (I
t1
). Region
4
represents the snap-back region, wherein the grounded-gate NMOSFET structure behaves as if it were a pure lateral bipolar transistor. The “holding voltage” of a grounded-gate NMOSFET structure can be determined by extrapolating Region
4
to the voltage axis using a linear scale graph.
It is desirable that MOSFET structures for use in ESD protection devices have a relatively low first breakdown point (i.e., relatively low V
t1
) to facilitate their transition into current conduction through a parasitic lateral bipolar mechanism. It is also desirable for such MOSFET structures to have a relatively low holding voltage, in order to lower their power dissipation, thereby increasing their ESD event survival expectancy.
The net dopant level in the N-type LDD drain extension region can be decreased to provide a more abrupt junction and thereby relatively low first breakdown voltage. However, since the N-type LDD source extension region and the N-type LDD drain extension region are formed simultaneously in conventional MOSFET structures, decreasing the net dopant level in the N-type LDD drain extension region simultaneously decreases the dopant level in the N-type LDD source extension region. Unfortunately, a decrease in the dopant level of the N-type LDD source extension region often results in an undesirable increase in the holding voltage, rather than the desired decrease in the holding voltage.
Still needed in the field, therefore, is a MOSFET structure for use in ESD devices that provides both a relatively low first breakdown point and a relatively low holding voltage.
SUMMARY OF THE INVENTION
The present invention provides a MOSFET structure for use in ESD protection devices that has both superior snap-back performance (i.e., a relatively low first breakdown voltage) and superior ESD event survival expectancy resulting from its relatively low holding voltage. These benefits of the present invention are attained by employing an LDD extension region that is adjacent only to the source region of the MOSFET structure (i.e., an LDD source extension region), without employing an LDD extension region adjacent to the drain region of the MOSFET structure. In other words, the conventional LDD drain extension region is absent in MOSFET structures for use in ESD protection devices according to the present invention.
The superior snap-back performance of MOSFET structures in accordance with the present invention is due to the junction between the drain region and the channel region, in the absence of an LDD drain extension region, exhibiting an abrupt junction breakdown behavior at a relatively low first breakdown voltage (V
t1
). In addition, the presence of an LDD source extension region reduces the source region barrier, thereby lowering the holding voltage and increasing ESD event survival expectancy.
MOSFET structures for use in an ESD protection device according to the present invention include a semiconductor substrate (e.g., a silicon substrate) of a first conductivity type (typically P-type) with a gate insulation layer (e.g., a gate silicon dioxide layer) disposed thereon. Also included are a patterned gate layer overlying the gate insulation layer, source and drain regions of a second conductivity type disposed in the semiconductor substrate and an LDD source extension region of the second conductivity type disposed in the semiconductor substrate adjacent to the source region. The MOSFET structure further includes a channel region of the first conductivity type disposed in the semiconductor substrate underneath the gate insulation layer and extending from the LDD source extension region to the drain region.
As described above, the absence of a LDD drain extension region combined with the presence of an LDD source extension region provides a MOSFET structure for use in an ESD protection device with a relatively low first breakdown voltage and a relatively low holding voltage.
Also provided is a method for manufacturing a MOSFET structure for use in ESD protection devices that includes steps of first providing a semiconductor substrate (e.g., a silicon substrate) with a gate insulation layer on its surface, followed by the formation of a patterned gate layer above the gate insulation
Carneiro Manuel
Hopper Peter J.
Nelms David
Nhu David
Pickering Mark C.
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