Method of screening non-volatile memory devices

Details Method of screening non-volatile memory devices Method of screening non-volatile memory devices

2002-02-06

2003-10-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S185330, C438S017000

Reexamination Certificate

active

06639860

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to screening of non-volatile memory devices, such as Flash memories.
BACKGROUND OF THE INVENTION
A screening test of non-volatile memory devices is commonly done at a high temperature in order to shorten the testing time. Once the test is completed, the memory devices that pass the test are marked and shipped to the customer. The invention relates to a screening test, which may be a part of all the tests for non-volatile memory devices, such as Flash memories. The test is used to remove or screen-out the die that has a defect or defects which occur during the fabrication of the memories.
Recently, it has been found that there is a plurality of defect modes in non-volatile memory devices. One mode of defect is a so-called “Hopping Conduction Model (HCM)”. When traps are generated in an oxide layer and the barrier is lowered, a small amount of leak current is generated thereat. Such a leak current is called SILC (Stress Induced Leakage Current), which is considered to be generated based on PCAT (positive charge-assisted tunneling) and neutral traps. When a leak current is generated, a voltage Vt is decreased.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide a method in which hopping conduction model of defects can be screened out reliably.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a memory device is controlled in temperature at a first level to carry out a first stage of screening; and then, at a second level to carry out a second stage of screening. Preferably, the first level of temperature is lower than the second level of temperature. The memory device may be a flash memory. The first and second levels of temperatures may be in ranges of 85 to 150° C. and 200 to 300° C., respectively.
For example, a method of screening out a non-volatile memory device, according to the present invention including the steps of: providing a semiconductor wafer including a plurality of flash memory devices thereon; setting and leaving the wafer in a first thermostatic oven controlled in temperature in a range of 85 to 150° C. for a predetermined period of time; taking out the wafer from the first thermostatic oven; setting and leaving the wafer in a second thermostatic oven controlled in temperature at about 250° C. for a predetermined period of time; taking out the wafer from the second thermostatic oven; and cooling down the wafer at a room temperature.
On the other hand, according to a conventional method of screening non-volatile memory devices, the wafer is controlled in temperature at a high temperature, for example, around 250° C. Since the hopping conduction model is caused by traps in the oxide layer, the hopping conduction model is not generated after the traps are removed or escaped. When a screening test is carried out in an atmosphere of over 200° C. , the traps generating the hopping conduction model are disappeared or removed before electrons of the memory cells are escaped.


REFERENCES:
patent: 5581510 (1996-12-01), Furusho et al.
patent: 5700698 (1997-12-01), Barsan et al.
patent: 6075724 (2000-06-01), Li et al.
patent: 07-045100 (1995-02-01), None

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