Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-27
2003-11-18
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C438S270000, C438S268000
Reexamination Certificate
active
06649973
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a power semiconductor device and a manufacturing method thereof, which is provided with a gate-driving element such as a longitudinal MOSFET and an insulated gate bipolar transistor (IGBT) in which a number of transistor cells of a so-called trench structure having a gate electrode formed in a trench formed from the surface of a semiconductor layer. More particularly, the present invention relates to a power gate driving semiconductor device and a manufacturing method thereof, which is allowed to have a reduced on-resistance by increasing the number of transistor cells per unit area so as to provide a great current and can be manufactured through a simple manufacturing process.
BACKGROUND OF THE INVENTION
Conventionally, with respect to a high-power gate-driving power MOS transistor, a construction in which a great number of transistor cells are formed in parallel with each other to form a matrix format has been adopted so as to provide a greater current. For example, as shown in
FIG. 7
, a transistor of a planar construction is formed in the following processes: an n-type semiconductor layer (epitaxial growth layer)
21
to be formed into a drain area is epitaxially grown on, for example, an n
+
-type semiconductor substrate
21
a
, and p-type impurities are diffused on its surface side so that a p-type body area
22
is formed, and an n
+
-type source area
23
is formed on the peripheral portion of the body area
22
. A gate electrode
25
is formed on the peripheral edge portion of the body area
22
and on the surface side of a semiconductor layer
21
located on the outside thereof through a gate oxide film
24
, and a channel region
22
a
is formed on the peripheral edge portion of the body area. Then, a source electrode (source wiring)
27
is formed to be connected to the source area
23
and the body area
22
by Al, etc., through a contact hole placed in the interlayer insulating film
26
, and a drain electrode
28
is formed on the rear face of the semiconductor substrate
21
a.
With respect to a power MOSFET having the trench structure in which gate electrodes are embedded in grooves formed in the semiconductor layer, as shown by an example in
FIG. 8
, trench are formed in a semiconductor layer
21
in a lattice shape, and after polysilicon to be formed into gate electrodes
25
have been embedded therein, a gate oxide film
24
is formed on the periphery thereof through oxidation, or after the gate oxide film
24
have been formed on the inner surface of the trench, polysilicon to be formed into gate electrodes
25
is embedded therein, so that the gate oxide film
24
and a gate electrode
25
are formed. Then, a p-type channel diffusion area
22
and an n
+
-type source area
23
are formed around the gate electrode
25
, and a channel region
22
a
is formed in the longitudinal direction. A source electrode
27
is formed so as to make an ohmic contact with the source area
23
and the channel diffusion area
22
, and a drain electrode
28
is formed on the rear surface of the semiconductor substrate
21
a
, in the same manner as FIG.
7
.
Here, the planar structure of the gate electrode in these transistors is formed into a desired shape, such as a square, a pentagon or a hexagon. Moreover, in most cases, these transistors are connected to an inductive load such as a motor, and in such a case, when the operation is turned off, an electromotive force tends to be applied thereto in the reverse direction, therefore, in order to prevent the transistor from destruction, as described above, the source electrode
27
is also allowed to contact the channel diffusion area
22
so that a protective diode in the reverse direction is formed between the source and the drain.
In the case of a large-current transistor as described above, it is important to make as many transistors cells as possible in a chip having a fixed size so as to decrease the on-resistance. In order to decrease the on-resistance, it is effective to make the channel width as wide as possible, and in the case of a transistor having the above-mentioned structure, it is preferable to make the total width (the length on the periphery of the gate electrode) of the channel region
22
a
formed on the periphery of the gate electrode as great as possible.
However, conventionally, in transistors of this type, since the source electrode is made in ohmic-contact with the channel diffusion area on the surface of the semiconductor layer, both of the source area and the channel diffusion area need to be exposed to the surface of the semiconductor layer, and since it is necessary to provide a margin used for a mask-superposing process upon diffusing to form the source area and a margin used for a mask-superposing process between a contact hole and a source area, the size C of the contact hole needs to be set to approximately 2 to 2.5 &mgr;m, for example, in the structure shown in
FIG. 8
, and the cell gap (pitch between the gate electrodes) A is limited to approximately 4.5 to 5 &mgr;m. In this case, the width B of the source area is set to approximately 0.8 to 1 &mgr;m. For this reason, it is not possible to sufficiently miniaturize the cell and to increase the number of cells, and the resulting problem is that it is not possible to sufficiently reduce the on-resistance.
SUMMARY OF THE INVENTION
The present invention has been devised to solve the above-mentioned problems, and its object is to provide a semiconductor device that is provided with an insulated gate-driving element of a trench construction or a planar-type, which reduces the on-resistance by increasing a gate width even with a chip area of the same size to provide a great current.
Another object of the present invention is to provide a manufacturing method of a semiconductor device which, in the case when there is an element which has the source electrode to be made in contact with both of a channel diffusion area and a source area, makes the source electrode in contact with these with a very small area by using a simple process.
Still another object of the present invention is to provide a manufacturing method of a semiconductor device which makes the source electrode in contact with both of the channel diffusion area and the source area while the pitch of the transistor cells is made very small, by allowing the source electrode to contact in a self alignment without the necessity of a mask alignment margin, and which is obtained by using a very small area through a simple process.
The inventors of the present invention have studied hard to provide a semiconductor device which minimizes the on-resistance of an insulation gate type semiconductor to obtain a great current with a small chip size, and have found that, although when, in general, a metal film such as Al is directly formed on the surface of a semiconductor layer as an electrode, it spikes into the semiconductor layer, resulting in a problem such as short-circuiting, a barrier metal layer is normally interposed in between, but the amount of the metal invading into the semiconductor layer due to the spike can be controlled by controlling conditions such as the thickness of the metal film to be formed and the thermal process, and the spiked alloy layer is sufficiently made in ohmic contact with the semiconductor layer.
Even in the case when the source electrode is made in contact with both of the source area and the channel diffusion area, the source area and the channel diffusion area are formed longitudinally so that the source electrode is allowed to spike into the channel diffusion area of the lower layer to provide superior ohmic contacts in both of the layers.
Moreover, by thickly oxidizing the gate electrode surface of the trench construction to provide an insulating film on the surface without forming a contact hole, even when the metal of the source electrode directly formed on the surface is allowed to spike, it is possible to make the metal in ohmic contact with both of the source area and the channel diffu
Everhart Caridad
Rabin & Berdo P.C.
Rohm & Co., Ltd.
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