Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2001-03-16
2003-10-28
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S318000, C430S319000, C174S250000
Reexamination Certificate
active
06638690
ABSTRACT:
The present invention relates to a method for producing multi-layer printed circuit boards.
Multi-layer printed circuit boards having a high wiring density have, in recent times, been advantageously produced by the so-called SBU (“sequential build-up”) method. The electrical connection between the individual conductors (“through-platings”) is customarily produced by means of drilled holes, which pass through the conductor planes and are metal-plated. The mechanically drilled holes are, however, relatively large (minimum diameter about 0.3 mm) and limit the wiring density of the printed circuit board. DE-A 38 40 207 describes a method for producing multi-layer printed circuit boards wherein through-platings of small diameter are produced photochemically with the aid of photoresist materials.
U.S. Pat. No. 5,451,721 also proposes an SBU method wherein through-platings are first established between the individual conductor planes using photoresists. Then, a conductive connection is produced between the outermost wiring layers by means of mechanically drilled and metal-plated through-holes. In the printed circuit board so produced, the two outer wiring layers are used for power supply lines whereas the signal wiring lines are located in the interior of the laminate.
The method described in U.S. Pat. No. 5,451,721 is, however, of only limited suitability for producing printed circuit boards having a disparate number of wiring layers on both sides of the laminate core because, in the case of the arrangement built up asymmetrically, a high degree of curvature is to be expected, especially when laminate cores less than 0.8 mm thick are used, caused by polymerisation shrinkage of the dielectric layer applied to only one side. In addition, copper-plating the copper layer on the rear one or more times results in disparate copper thicknesses on both sides of the board. The subsequent etching customarily carried out simultaneously on both sides results in over-etching of the upper, thinner copper layer.
The aim of the invention was to develop a method for producing sequentially built-up printed circuit boards having a disparate number of conduction planes on both sides of the laminate core that does not have the above-mentioned disadvantages.
It has now been found that satisfactory results are obtained by starting from a laminate core that has conductor structures on only one side, coating that core on both sides with a dielectric, but structuring only one side and fully curing the other side.
The present invention accordingly relates to a method for producing sequentially built-up printed circuit boards having a disparate number of conduction planes on both sides of the laminate core, which method comprises the following method steps:
(A) coating both sides of a printed circuit board having conductor structures on only one side with a dielectric comprising a photopolymer or a thermally curable polymer;
(B) structuring the plating holes (vias) on the side having the conductor structures by exposing the dielectric comprising a photopolymer to light and then developing with a solvent or by laser-drilling the plating holes (vias) into the dielectric comprising a thermally cured polymer;
(C) depositing a copper layer on both sides of the board so obtained;
(D) forming conductor structures on the front and completely etching away on the rear, if further asymmetric build-up is to be carried out, or on both sides of the printed circuit board if there is to be no further build-up or if further build-up is to be carried out symmetrically, by means of selective etching with the aid of resists;
(E) repetition of process steps (A) to (D) if further asymmetric build-up is to be carried out or (A) and subsequent structuring (F) of the dielectric layer on both sides followed by (C) and (D) if further build-up is to be carried out symmetrically.
REFERENCES:
patent: 4780957 (1988-11-01), Shiga et al.
patent: 5451721 (1995-09-01), Tsukada et al.
patent: 5476748 (1995-12-01), Steinmann et al.
patent: 5532105 (1996-07-01), Yamadera et al.
patent: 5945258 (1999-08-01), Shimizu et al.
patent: 3840207 (1990-05-01), None
Y. Tsukada et al., “Surface laminar Circuit Packaging” XP 000473962, pub. May 18, 1992, pp. 22-27.
Meier Kurt
Münzel Norbert
Huff Mark F.
Proskauer Rose LLP
Sagar Kripa
Vantico Inc.
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