Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-12-29
2003-12-09
Lane, Jack A. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S156000
Reexamination Certificate
active
06662276
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to computer architecture. In particular, the invention relates to Non Uniform Memory Architecture (NUMA) systems.
2. Description of Related Art
Non Uniform Memory Architecture (NUMA) systems have been increasingly popular in recent years. A NUMA system typically consists of a number of nodes connected through interconnecting links and/or switches. Each node may have one or more processors and node memory as part of the system overall memory.
To maintain cache coherency, NUMA systems employ specialized cache coherency protocols. NUMA coherency protocols use hardware data structures called directories to keep track of the sharing information for each memory block. The sharing information for a block consists of the block caching state and the identity of the nodes that share this block. Typically, the directory is distributed among the NUMA nodes with each node being responsible for keeping track of the sharing information for the portion of the memory blocks located on the particular node.
The directory protocol is implemented by the directory controller. Nodes that wish to access a particular memory block must send a message to the directory controller in order to request permission to access the block. The directory controller performs all the necessary protocol actions to ensure that cache coherency is not violated in the system.
Previous NUMA systems have implemented directories in two ways: full and sparse directory systems. Full directory systems store the sharing information next to each block in main memory. A full directory wastes a significant amount of physical memory since a directory entry is required for each and every memory block in main memory even if the memory block is not cached anywhere in the system. Furthermore, accessing the main memory for each directory protocol action can adversely impact the performance of the directory protocol.
Sparse directory systems only store the sharing information for memory blocks currently cached in remote processors. In sparse directories, the amount of memory used to keep the sharing information is directly proportional to the number of memory blocks that can be stored in the cache of an individual processor. Existing implementation of sparse directory systems use separate random access memory (RAM) devices interfaced to the directory controller. This results in inefficient use of hardware and reduces performance.
REFERENCES:
patent: 5893144 (1999-04-01), Wood et al.
patent: 5926829 (1999-07-01), Hagersten et al.
patent: 6275900 (2001-08-01), Liberty
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