Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-04-10
2003-10-07
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S748000, C235S449000, C235S488000, C235S492000, C235S493000
Reexamination Certificate
active
06631479
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing system method and apparatus and in particular to method and apparatus for processing a series of mutually related data.
2. Description of the Related Art
IC cards are used as identification tags for credit cards or when circulating and distributing goods. The circuit shown in
FIG. 12
is a known logic process circuit conventionally used for IC cards. The logic process circuit
2
in
FIG. 12
is composed of a combinational logic block CB that comprises NAND circuits and OR circuits, etc., and a latch block LT that latches an output of the combinational logic block CB.
The combinational logic block CB executes a prescribed logic operation in response to input data IN and outputs an operational result OUT. The latch block LT latches the operational result OUT when a clock pulse C
p
rises (or falls) and subsequently output an output Q.
By using the logic process circuit
2
, each operational result OUT is latched as the clock pulse C
p
rises (or falls) and the latched operational result can be output while the clock pulse C
p
is “H” (or “L”). Consequently, noise is eliminated from the operational result and a stable output can be obtained. Accordingly, by using a plurality of the logic process circuits
2
in a combination, a highly reliable sequential logic processing can be performed.
Conventional logic process circuits
2
, however, have had the following problems. In conventional logic process circuits, a voltage had to be consistently applied to the circuits to retain the data that were being processed. Therefore, if a power failure occurs in the midst of a logic operation, the operational results prior to the power failure were not recovered even when the power source was restored.
In a sequential logic processing, i.e., receiving a series of mutually related data from a host computer (not shown in
FIG. 12
) and sequentially processing them, the prior processing must be used for the succeeding processing. If the power source failed during the sequential logic processing in the conventional logic process circuits, the entire series of data had to be reprocessed. Therefore, the process lacked reliability and was wasteful.
Particularly, the power supply of non-contact IC cards, etc., was easily disturbed since the power was supplied through radio waves. As a result, when the volume of a series of data to be sequentially processed was high, a sequential logic processing had to be frequently repeated. In consequence, the sequential logic processing often took a long time to complete.
SUMMARY OF THE INVENTION
An object of the present invention is to solve these and other problems associated with conventional logic process circuits and provide a data processing system, data processor, and data processing method that can process a series of mutually related data quickly.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a data processing system that can divide a series of mutually related data into a number of data groups and sequentially process the series of data.
The data processing system in accordance with the present invention comprises a process output circuit which processes and outputs input data, a memory device which stores data, and a process control device which detects whether or not the present data group is processed by the process output circuit successfully. When the process control device detects that a process has been successful, it stores the present data group in the memory device and causes the process output circuit to continuously process the next data group. On the other hand, when the process control device detects that a process has failed, it causes the process output circuit to output the processing result of the preceding data group stored in the memory device and to continuously reprocess the present data.
In another aspect, the present invention provides a method for data processing which sequentially processes a series of mutually related data by dividing the series into a number of data groups. The method for data processing in accordance with the present invention comprises the step of storing the present data group and causing the process output circuit to continuously process the next data group when the process control device detects that the process has been successful. Moreover, the method for data processing in accordance with the present invention also comprises the step of causing the processing result of the stored preceding data group to be output and causing the present data to be continuously reprocessed when the process control device detects that the process has failed.
Therefore, it is not necessary to reprocess the entire series of data from the beginning even when the process of the present data group fails because the present invention allows the process to resume from the present data group. Accordingly, the process can continuously process mutually related data without wasting the proceeding results prior to the moment of failure.
Moreover, a number of rewriting contents stored in the memory device is minimized because only the processing results of the present data group, not the entire processing results processed until the moment of the power failure, are stored. In consequence, even if some time must be spent rewriting the stored contents, the total data processing time can be shortened compared to the time it would take in case the entire processing results must be reprocessed. In addition, a high speed rewritable memory device can be used since there is no restriction on the number of rewriting. In other words, the present invention allows a series of mutually related data to be processed quickly.
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Patterson et al., Computer Organization & Design The Hardware/Software Interface, 1998, Morgan Kaufmann Publishers, Inc., Second Edition, pp. 436-465.
Beausoliel Robert
Hogan & Hartson LLP
Maskulinski Michael
Rohm Co., LTD
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