Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2001-08-10
2003-10-28
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S734000, C257S737000
Reexamination Certificate
active
06639315
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a small semiconductor device having external terminals electrically connected to a semiconductor element, and to a mounted semiconductor device structure made by mounting this semiconductor device to a printed circuit board.
In recent years, as portable terminals have spread and accompanying reduction in the size and weight of various appliances using semiconductor devices has progressed, the development of semiconductor devices to facilitate this size reduction has become necessary.
In this connection, there is technology which aims to make the size of a semiconductor device approach the size of the semiconductor element on which it is based. A semiconductor device package based on this kind of technology is generally called A-CSP (Chip Size Package, or Chip Scale Package). In a typical CSP structure, metal bumps are disposed within the area of the face of the semiconductor element, and the semiconductor element is-mounted to a printed circuit board by way of these metal bumps. Solder is the material most commonly used for the metal bumps.
In a mounted semiconductor device structure made by mounting a CSP to a board like this, when a temperature change is applied, due to a linear expansion coefficient differential between the semiconductor element and the board, differential thermal expansion arises. Consequently, a thermal distortion occurs repeatedly in the solder bumps sandwiched between the semiconductor element and the board, and the solder bumps may suffer fatigue failure. Accordingly, securing a long life for solder connections in temperature cycle tests is an issue. As an example of a CSP in related art designed with the life of its solder parts in mind, in International Patent Publication No. 504408/1994 there is disclosed a CSP of a structure wherein a tape carrying external terminals is set on a cushion material (an elastomer resin) on the face of a semiconductor element on which a circuit is formed, and the external terminals are electrically connected to the electrodes of the semiconductor element. Because the soft elastomer resin deforms and absorbs thermal distortions, distortions arising in the solder bumps are reduced and their life is increased.
In Japanese Patent Laid-Open No. 224259/1994, a structure is disclosed wherein a semiconductor element is mounted on a ceramic board provided with through holes; electrodes are provided on the other side of the ceramic board; and this is mounted to a printed circuit board. In order to connect the semiconductor device to the printed circuit board via a ceramic board, since the structure reduces the area of electrodes for wire bonding around the semiconductor, the semiconductor package can become reduced in size.
Numerous semiconductor elements are formed at once on a single wafer, and each of the CSP examples above is based on the premise that individual semiconductor elements are processed after being cut from the wafer.
In recent years, technology has been developed for fabricating small semiconductor devices of the same size as their semiconductor elements at a lower cost by carrying out packaging operations on a plurality of semiconductor elements that are still in the wafer.
An example of a CSP which can be fabricated while still in the wafer state is proposed in Nikkei Micro Devices, April 1998: “New Method for Cheaply Making Promising Candidate CSP for Chip Size Mounting” (page 164 to page 167). In the semiconductor device discussed in this article, further interconnections are formed on the semiconductor element; metal via posts of height about 100 &mgr;m in height are formed on these interconnections; the space around the via posts is sealed with resin; and metal bumps are formed on the upper faces of the via posts with a barrier metal layer therebetween. A temporary film is spread on the face of via posts in a metallic mold in a process of sealing with resin, so the metallic mold can be removed easily from the sealing resin after pouring into the mold.
In a semiconductor device disclosed in Japanese Patent Laid-open No. 54649/1999, a low elastic modulus layer is formed on the main face of the semiconductor element with an opening over an electrode region where element electrodes are disposed; lands to constitute external electrodes are formed on the low elastic modulus layer; a metal interconnection pattern in which pads on the element electrodes are integrated with the lands and metal interconnections connecting them together is constructed; the surface is covered with solder resist; openings are formed above the lands, and metal balls are joined to the lands.
In this construction, thermal stresses can be absorbed by deformation of the low elastic modulus layer. And because the edges of the opening in the low elastic modulus layer are worked to sloping face shapes, stress concentrations in the metal interconnections are avoided and breakages are prevented.
Also, a passivation film for protecting the semiconductor element may be further provided in a region of the main face of the semiconductor element, excluding the pads. With this related art technology, it is considered that, if a modulus layer is used which is sufficiently low in elastic, modulus and sufficiently thick, the stress-moderating effect is higher than that of the structure described above using sealing resin.
In Japanese Patent Laid-Open No. 204560/1999 there is mentioned a structure wherein, in addition to the structure described above, a resin layer having a linear expansion coefficient between the linear expansion coefficients of the semiconductor element and the low elastic modulus layer is interposed between the two to prevent detachment from each other.
However, in the related art semiconductor devices described above, the following problems may arise.
In the related art semiconductor device discussed above, stresses caused by differential thermal expansion between the semiconductor element and the board on which it is mounted are absorbed by elastic deformation of a low elastic modulus layer; however, to secure sufficient reliability of the metal bumps by this method, it is likely that it will be necessary to make the low elastic modulus layer considerably thick.
In a related art semiconductor device above, a thickness of 10 to 150 &mgr;m is considered desirable. And, the opening is formed after the low elastic modulus layer is first formed flat, and exposed, for example, by using scattered light so that the side faces of the opening are not vertical, but rather are sloping.
However, when this kind of process is carried out on a thick film of, for example, a thickness of 100 &mgr;m or more, to control the shape of the side faces and to control the bottom end of the opening to dimensions close to the edge of a fine element electrode requires extremely high-precision working technology.
When considered to be semiconductor devices are manufactured on in the related art, at the stage of forming the thick low elastic modulus layer over the entire face of the wafer, the wafer warps severely. As a result, carrying out the highly precise working mentioned above on all of the chips on the warped wafer-is difficult.
Also, as another issue, in a CSP fabricated at the wafer level, there is the problem of its electrical characteristics. That is, when manufacturing a CSP at the wafer level, as a result of problems such as warping of the wafer, it is difficult to form a very thick resin layer, and the insulating layer interposed between the interconnections of the package and the semiconductor element tend to become thin, and the interconnection capacitance tends to become large.
When the interconnection capacitance becomes large, severe noise arises in the signal lines, and there is a risk of the device malfunctioning. Consequently, securing the thickness of the insulating film between the package interconnections and the semiconductor element surface becomes an issue.
The technology set forth in Japanese Patent Laid-Open No. 204560/1999 relates to a semiconductor device wherein a resin layer is
Kazama Atsushi
Miura Hideo
Yaguchi Akihiro
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