Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-06
2003-02-11
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S647000, C257S648000, C257S652000, C257S635000, C257S510000, C257S513000, C257S519000, C257S397000, C257S410000, C257S295000, C257S411000, C257S310000, C257S324000, C257S325000, C257S405000
Reexamination Certificate
active
06518635
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to an improved semiconductor device so as to be able to ease gate electric field concentration at an isolation edge. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIGS. 48
to
52
show steps of a conventional semiconductor device manufacturing method disclosed in 28. 1. 1 of International Electron Device Meeting (IEDM) 94 (1994).
Referring to
FIG. 48
, a pattern of a thermal oxide film
101
and a silicon nitride film
102
is formed on a silicon substrate
100
. A portion without the pattern is intended to isolate electric field transistors (MOSFETs) (active elements). The opening portion (isolation portion) is formed such as by photolithography and dry etching. In other words, the pattern is removed at a portion for forming an isolation region and is left at a portion for forming an electronic element. By using the pattern of silicon nitride film
102
, silicon substrate
100
is selectively etched to form a trench
103
at a portion to be an isolation region.
Referring to
FIG. 49
, a thermal oxide film
104
is formed on an inner wall of trench
103
by thermal oxidation. Thermal oxidation film
104
is formed since silicon on the surface of trench
103
becomes an oxide film through oxidation. Thereafter, trench
103
is filled with an oxide film
105
(tetraethoxysilane (TEOS) or high density plasma (IIDP)—CVD, for example).
Referring to
FIG. 50
, a planarization method (such as etching and chemical mechanical polishing) is used to reduce the thickness of oxide film
105
toward the substrate by using silicon nitride film
102
as a stopper so as to planarize the surface of the semiconductor device. Silicon nitride film
102
which is exposed by planarization is removed. Finally, oxide film
101
is removed by wet etching.
Referring to
FIG. 51
, a gate insulation film
107
is formed on silicon substrate
100
. In this case, gate insulation film
107
is formed by thermal oxidation so that the dielectric constant in the channel direction becomes uniform.
Referring to
FIG. 52
, a gate electrode material layer
108
is formed on silicon substrate
100
to complete a gate electrode of the transistor.
In the following, problems with the conventional art will be described.
FIG. 53
is an enlarged view of a portion encircled in FIG.
51
. In trench isolation provided by the conventional method, a depression
109
is formed at an isolation edge. If gate electrode
108
is formed in this state, the gate electrode is also formed in depression
109
. Since the gate electric field influences portion
109
from two directions of A, B in the figure, the electric field becomes stronger at portion
109
than the channel central portion.
Considering transistor operation, the entire channel should start operation simultaneously. However, a transistor having such a structure starts its operation from a portion with a stronger gate electric field, which results in irregular transistor operation. Since this results in decrease in a threshold voltage and increase in leakage current during MOSFET operation, it becomes a reason for the deteriorated MOSFET properties. Even if there is not any depression, such deterioration of the MOSFET properties is caused depending on a manner in which the gate electric field is applied.
SUMMARY OF THE INVENTION
The present invention was made to solve the above described problems, and its object is to provide an improved semiconductor device so as to be able to ease gate electric field concentration at an isolation edge (channel edge).
Another object of the present invention is to provide an improved semiconductor device so as to be able to suppress decrease in a threshold during MOSFET operation.
Still another object of the present invention is to provide an improved semiconductor device so as to be able to reduce leakage current.
The present invention also provides a method of manufacturing such a semiconductor device.
A semiconductor device according to a first aspect includes a semiconductor substrate. A gate insulation film is formed on the semiconductor substrate. A gate electrode is formed on the semiconductor substrate with the gate insulation film therebetween. The dielectric constant of the gate insulation film is not uniform in the surface.
In the semiconductor device according to a second aspect, the dielectric constant of the gate insulation film is not uniform in the channel width direction.
In the semiconductor device according to a third aspect, the dielectric constant of a channel edge, in the channel width direction, of the gate insulation film is made lower than that of a channel central region.
In the semiconductor device according to a fourth aspect, the dielectric constant of the channel central region of the gate insulation film is made higher than 3.9 which is the dielectric constant of an ordinary oxide film.
In the semiconductor device according to a fifth aspect, the channel edge, in the channel width direction, of the gate insulation film includes F or C.
In the semiconductor device according to a sixth aspect, the channel central region of the gate insulation film includes N.
In the semiconductor device according to a seventh aspect, the gate insulation film is formed of Ta
2
O
5
or (Ba, Sr) TiO
3
.
In a semiconductor device manufacturing method according to an eighth aspect, a gate insulation film having a lower dielectric constant at its channel edge that at its channel region is formed on a semiconductor substrate.
In the semiconductor device manufacturing method according to a ninth aspect, a first material layer of at least one stacked layer is first formed on a semiconductor substrate. In the first material layer, an opening portion for forming an isolation region is formed. By using the first material layer, in which the opening portion is formed, as a mask, a surface of the semiconductor substrate is etched to form a trench at the surface of the semiconductor substrate. Ions for decreasing the dielectric constant are implanted into a sidewall of the trench. To fill in the trench, a second material layer is formed on the semiconductor substrate. The thickness of the second material layer is reduced toward the substrate till a surface of the first material layer is exposed. The first material layer thus exposed is removed. A gate insulation film is formed on the semiconductor substrate. A gate electrode is formed on the gate insulation film.
In the semiconductor device manufacturing method according to a tenth aspect, a first material layer of at least one stacked layer is first formed on a semiconductor substrate (first step). In the first material layer, an opening portion for forming an isolation region is formed (second step). By using the first material layer, in which the opening portion is formed, as a mask, a surface of the semiconductor substrate is etched to form a trench at the surface of the semiconductor substrate (third step). To fill in the trench, a second material layer is formed on the semiconductor substrate (fourth step). The thickness of the second material layer is reduced toward the substrate till a surface to the first material layer is exposed (fifth step). Ions for decreasing the dielectric constant are implanted into the second material layer filled in the trench (sixth step). The first material layer thus exposed is removed (seventh step). A gate insulation film is formed on the semiconductor substrate (eighth step). A gate electrode is formed on the gate insulation film (ninth step).
In the semiconductor device manufacturing method according to an eleventh aspect, the ions are implanted obliquely to the semiconductor substrate in the sixth step of the ninth aspect.
In the semiconductor device manufacturing method according to a twelfth aspect, a first material layer of at least one stacked layer is first formed on a semiconductor substrate. In the first material layer
Abe Yuji
Oishi Toshiyuki
Shiozawa Katsuomi
Tokuda Yasunori
Lee Eddie
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Joseph
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