Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-29
2003-12-30
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S382000
Reexamination Certificate
active
06670682
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor memory devices, and more particularly, to a structure having improved burn-in reliability and refresh characteristics in dynamic random access memory (DRAM) devices and a method of making it.
Metal oxide semiconductor (MOS) structures are basic electronic devices used in many integrated circuit (IC) devices. One such structure is the metal oxide semiconductor field effect transistor (MOSFET), which is typically formed in a semiconductor substrate by providing a gate structure over the substrate to define a channel region, and by forming source/drain regions on opposing sides of the channel region. To keep pace with the current trend toward maximizing the number of circuit devices contained in a single chip, integrated circuit designers continue to design IC devices with smaller and smaller feature sizes. The current state of the art for production MOSFET devices includes physical gate lengths of less than about 0.18 micron (&mgr;m).
To help explain problems associated with prior art MOSFET structures, a cross section of a typical MOSFET device is shown in FIG.
1
. In addition, various components of device leakage current are schematically represented. The total device leakage current, I
off
, is comprised of three major components: device off-current I
1
, gate leakage I
2
, and thermal and tunneling junction leakage &agr;I
3
. The device off-current I
1
, is determined by the physical gate length L
gate
and the channel width (W) of the device, with the gate voltage V
g
=0 V, the drain voltage (V
d
)=power-supply voltage (V
dd
), and the source voltage (V
s
) to ground. The gate leakage current, I
2
, is determined by the gate-oxide thickness (T
ox
), power-supply voltage (V
dd
), and the total gate area (L
gate
×W). The thermal and tunneling junction leakage, I
3
, is determined by the operating temperature of the device and the total doping level in the substrate, which is one reason the lightly doped regions are typically placed adjacent the channel region in order to minimize junction leakage. The device off-state leakage current, I
off
, also known as the subthreshold leakage current, is a function of L
gate
, temperature (T), and power-supply voltage (V
dd
). The subthreshold leakage current of a MOS transistor with a physical gate length (L
gate
) of less than 0.18 &mgr;m exhibits what is called drain induced barrier lowering (DIBL) effect. The DIBL effect results in: (1) the leakage current changing exponentially in proportion to the drain voltage as well as the gate voltage, and (2) with the increase in the substrate bias, the drain voltage dependency increases.
As the channel lengths of MOSFET devices have been reduced below 0.18 &mgr;m, MOSFETS have become more susceptible to certain problems. One common problem is increased junction leakage I
3
, which affects the refresh characteristics of a dynamic random access memory (DRAM) cell. DRAM is a specific category of random access memory (RAM) containing an array of individual memory cells, where each memory cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. Due to junction leakage, the stored charge must be refreshed in the capacitor on a periodic basis. Increased junction leakage leads to a premature depletion of the capacitor's stored charge, necessitating more frequent refresh cycles in such DRAM devices.
Additionally, with gate lengths of less than 0.18 &mgr;m, the width of the gate overlap region (
FIG. 1
) in such transistors should be as small as possible due to very tight limitations on allowable sub-threshold leakage currents. Having a smaller gate overlap region width provides an effective gate length that is as large as possible for a given physical gate length, which reduces drain-induced barrier lowering. Reducing drain-induced barrier lower improves the refresh characteristics for DRAM devices with gate overlap regions of less than 0.018 &mgr;m.
However, reducing the width of the gate overlap region is not without consequences. In particular, reducing the width of the gate overlap region worsens the reliability of the DRAM device after a high voltage stress, such as experienced during burn-in. Burn-in is the application of thermal and electrical stresses for inducing the failure of marginal memory devices, those with inherent defects or defects resulting from manufacturing aberrations which cause time and stress dependent failures. During burn-in testing, ambient heat and the heat caused by the current flow under the gate structure of each MOS transistor stress the device by raising the junction temperature. This stress can lead to the premature failure of weaker devices, as the heat of burn-in causes ions in the active regions of each MOS transistor to dissipate to the point where the device can no longer function.
Generally, gate overlap widths greater than 0.02 &mgr;m make DRAM devices more robust to reliability stressing, such as burn-in testing, because the gate structure has control over the inversion region directly beneath the gate structure. In such devices, the gate structure can compensate for any charges that are trapped in the gate oxide interface due to the high electrical field. That is, the gate overlap regions are less likely to degrade when high voltage is applied to the device, such as the types of voltages applied during burn-in or other manufacturing stress testing. For an NMOS device having a gate length less than 0.18 &mgr;m, a gate-to-substrate voltage greater than the threshold voltage, such as experienced during burn-in, causes the formation of an inversion layer of free electrons (conducting channel) in the p-type substrate. Accordingly, a DRAM device with a gate overlap region width less than 0.018 &mgr;m, which places the peak electric field outside the overlap region, results in the gate structure having less control over the inversion region, thereby further degrading device lifetime significantly. It is to be appreciated that device lifetime is generally defined as a percentage change in transconductance or drain saturation current.
To further illustrate this point,
FIGS. 13
a
and
13
b
, are graphs each showing a family of drain current (I
d
) versus drain voltage (V
d
) characteristics for different gate voltages (V
g
).
FIG. 13
a
illustrates the I
d
/V
d
response of a poorly designed device, which shows degradation (i.e., low I
d
) after the first V
g
sweep and is one of the main reasons for failure at burn-in.
FIG. 13
b
, on the other hand, illustrates well-behaved I
d
/V
d
curves for all V
g
sweeps.
As mentioned previously, to reduce junction leakage DRAM devices are often designed so that their source/drain regions have a minimum dopant density. However, a lightly doped source/drain region is easy to deplete even with a small trapped-charge density at the gate oxide interface. Accordingly, device reliability decreases further in devices with gate overlap region widths less than 0.018 &mgr;m by increasing the threshold voltage and transconductance after a high voltage stress, such as a device is subjected to during burn-in.
Further aggravating the problems associated with such devices with reduced overlap gate regions, is BPSG poisoning and access device n-sheet resistance. Rich BPSG (boronphosphosilicate glass) layers are needed for easy re-flow and planarity in the device. This is particularly important in stacked DRAM cell technology where the DRAM capacitor is formed in a very tall stack above the silicon substrate. Thin nitride or TEOS liners are needed for better contact processing, such as for forming precisely sized plug openings. However, TEOS liners can potentially increase the trapped states and interfacial charge density close to the source/drain regions. TEOS liners that reduce the interfacial oxide layer (gate oxide plus reoxidation) thickness in NMOS devices can permit boron from a BPSG layer to diffuse through the thin TEOS liner to compensate the n-type dopant in a so
Dinsmore & Shohl
Micro)n Technology, Inc.
Ngo Ngan V.
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