Semiconductor device with groove type channel structure

Details Semiconductor device with groove type channel structure Semiconductor device with groove type channel structure

2002-12-30

2003-12-16

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S244000, C257S334000, C257S466000, C257S618000, C257S622000, C438S259000, C438S270000, C438S271000, C438S589000

Reexamination Certificate

active

06664592

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and, more particularly, to a manufacturing method of manufacturing a semiconductor device which includes a step of forming a dummy gate.
To implement a higher performance and lower cost of a semiconductor integrated circuit using MOS transistors, miniaturization of devices is important. The miniaturization of devices, which can be accomplished by using the STI (Shallow Trench Isolation) technique, faces a problem of an increased wiring resistance. To overcome this problem, a scheme of reducing the wiring resistance using a metal material of a low resistance for the gate electrode has been proposed.
In a conventional case where a source/drain region is formed after forming a gate insulator film and a gate electrode, a high temperature treatment and thermal oxididation are required, which raise such problems as the increased resistance of the metal electrode and deterioration of the reliability of the gate insulator film.
As means of overcoming those problems, a step of forming a source/drain region, which involves a high temperature treatment, is carried out prior to burying the gate insulator film and gate electrode in a groove which is self-aligned with the source/drain region.
Referring to
FIGS. 1A through 1I
,
2
A and
2
B, one example of this technique (Jpn. Pat. Appln. No. 8-356493) will be discussed below.
FIGS. 1A through 1I
illustrate the cross-section of a transistor in a gate length direction (channel length direction), and
FIGS. 2A and 2B
illustrate the cross-section of the transistor in a gate width direction (channel width direction).
First, using the shallow trench isolation (STI) technique, a transistor-forming region
502
and an isolation region
503
are formed on an Si substrate
501
(FIGS.
1
A and
2
A).
Next, an SiO
2
film
504
of about 10 nm in thickness is formed on the exposed surface of the Si substrate
501
, and a poly Si film for a dummy gate pattern is deposited about 300 nm thick on this SiO
2
film
504
and is processed to form a dummy gate pattern
505
using, for example, lithography and RIE (FIG.
1
B).
Then, with the dummy gate pattern
505
used as a mask, phosphorous ions, for example, are injected in a device region surrounded by the isolation region
503
to form an n
−
type diffusion region
506
(FIG.
1
C).
After an Si
3
N
4
film is deposited on the entire surface, RIE is performed on the entire surface to form an Si
3
N
4
film
507
with a thickness of approximately 20 nm on the side wall of the dummy gate pattern
505
(FIG.
1
D).
Then, with the dummy gate pattern
505
and the Si
3
N
4
film
507
used as masks, arsenic ions, for example, are injected in the n
−
type diffusion region
506
, forming an n
+
type diffusion region
508
, thus forming or a so-called LDD (Lightly Doped Drain) structure (FIG.
1
E).
Next, a CVD-SiO
2
film
509
is deposited, for example, about 300 nm thick on the entire surface, and is densified for approximately 30 minutes in the N
2
atmosphere at about 800° C., after which the entire surface is flattened by CMP (Chemical Mechanical Polishing) to expose the surface of the dummy gate pattern
505
(FIG.
1
F).
Then, the dummy gate pattern
505
is selectively removed to form a groove
510
, after which with a resist film (not shown) formed on a desired region, an interlayer film (SiO
2
film
509
) and a sidewall insulator film (Si
3
N
4
film
507
) used as masks, ion injection is carried out only in the channel reserved region under the groove
510
. The activation of this channel impurity is implemented by a heat treatment at 800° C. for about 10 seconds using RTA, for example, thereby forming a channel impurity region
511
(FIG.
1
G).
Then, the SiO
2
film
504
at the bottom of the groove
510
is removed (FIGS.
1
H and
2
B).
Next, a high dielectric film, such as a Ta
2
O
5
film, is deposited about 20 nm thick as a gate insulator film
512
on the entire surface, followed by deposition of a metal film of Ru or the like on the entire surface as a gate electrode
513
. Thereafter, CMP is performed on the entire surface to leave the metal electrode
513
and the high-dielectric gate film
512
buried in the groove
510
(FIG.
1
I).
Thereafter, after an SiO
2
film is deposited about 200 nm thick as an interlayer insulator film on the entire surface, contact holes to the source and drain regions and the gate electrode are formed in the interlayer insulator film, then an Al layer is formed on the entire surface and patterned to form Al wiring. Then, a passivation film is deposited on the entire surface, which completes the basic structure of a transistor.
Since this method however exposes the end portions of the isolation region twice as shown in
FIGS. 2A and 2B
, etching with, for example, a fluorine-based etching solution would form large dents at those portions, thus exposing the edge cornets of the device region. As a result, an electric field is concentrated on the edge corners, resulting in deterioration of the transistor characteristics, such as a lower reliability of the gate insulator film.
In the conventional transistor manufacturing method which forms a source/drain region using a dummy gate pattern and then forming a gate insulator film and a gate electrode in a groove formed by removing the dummy gate pattern, large dents are formed at the edge corners of the isolation region, exposing the edge corners of the device region, so that an electric field is concentrated on the edge corners, deteriorating the transistor characteristics.
A description will now be given of other problems of a manufacturing process for an MOS transistor using a dummy gate.
The first problem will be discussed below.
In a manufacturing process for MOS transistor to be used in a DRAM or the like, as shown in
FIG. 3A
, a sidewall insulator film
507
having an etching-resistive property is formed on the side surface of a dummy gate
505
, so that even with slight misalignment at the time of forming contact holes to the gate electrode and the source and drain regions in an interlayer insulator film which will be formed later, the sidewall insulator film
507
prevents the gate electrode and the source/drain region from being short-circuited and thus improves the integration density.
In a manufacturing process for damascene gate transistors, conventionally, to form the sidewall insulator film
507
on the side surface (where an oxide film is formed) of the dummy gate
505
, which is comprised of an amorphous silicon film
505
a
and a silicon nitride film
505
b
, the height of the sidewall insulator film
507
should be controlled by RIE that is carried out to form the sidewall insulator film
507
, at the time of performing CMP on the interlayer insulator film, so that the sidewall insulator film
507
will not be exposed when the CMP is completed.
When the sidewall insulator film
507
is exposed upon completion of CMP as shown in
FIG. 3B
, however, the sidewall insulator film
507
may be removed at the time of removing the dummy gate
505
as shown in FIG.
3
C. That is, the margin for a fluctuation in etching result was low.
In the case of ordinary transistors, when a silicon nitride film is used as an etching stopper to be formed on the gate electrode and the sidewall insulator film
507
of the gate electrode, the parasitic capacitance may not become low enough to meet the requirements of ultra-miniaturization and fast operation because the dielectric constant of the silicon nitride film is not so low.
The second problem will be discussed below.
In the manufacturing process for damascene gate transistors, since the dummy gate also serves as a CMP stopper at the time of flattening the interlayer insulator film, the silicon nitride film
505
b
is used for the dummy gate (
FIG. 4A
) as in the example illustrated in
FIGS. 3A-3C
. Normally, a silicon nitride film
520
is a typical liner to be formed on the side wall of the dummy gate
505
. In the case of

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