Method and circuitry for clock synchronization

Details Method and circuitry for clock synchronization Method and circuitry for clock synchronization

1994-11-29

1996-01-16

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327144, H04C 700

Patent

active

054854903

ABSTRACT:
Circuitry for performing fine phase adjustment within a phase locked loop is described. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The affect of the even phase signal and the odd phase signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. The weighting signals prevent glitches from appearing on the output signal when either the even phase signal or the odd phase signal is switching. A method of performing fine phase adjustment in a phase locked loop is also described.

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Stanley G. Burns, et al., Principles of Electric Circuits, "Differential Amplifier with Active Loading", 1987, pp. 554-559.

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