Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-03-12
2003-11-11
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
Reexamination Certificate
active
06646936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor module including a plurality of such semiconductor memory devices, and particularly relates to the semiconductor memory device, which can enter a test mode in the module, as well as the semiconductor module.
2. Description of the Background Art
In recent years, attention has been given to a DIMM (Double Inline Memory Module), which operates in synchronization with a clock signal having a frequency of 50 MHz or more. The DIMM has two semiconductor modules formed on the opposite sides of one substrate, respectively. The semiconductor module includes a plurality of DRAMs (Dynamic Random Access Memories).
In particular, the semiconductor module used in a registered DIMM (RDIMM) includes a plurality of DRAMs, and is configured to perform input/output of data to and from the DRAMs in synchronization with a clock signal having a high frequency of 50 MHz or more.
Referring to
FIG. 33
, a semiconductor module
620
used in an RDIMM includes DRAMs
631
-
639
, registered buffers
650
and
660
, and a PLL circuit
670
. Semiconductor module
630
used in the RDIMM includes DRAMs
640
-
648
.
PLL circuit
670
generates a clock signal having a high frequency of 50 MHz or more and adjusts timing, according to which input signals are applied to DRAMs
631
-
648
.
Referring to
FIG. 34
, each of registered buffer circuits
650
and
660
receives the control signal, and address signal, which are externally applied, and coverts the voltage levels forming the control signals to the voltage levels to be used in corresponding semiconductor module
620
or
630
for applying them to DRAMs
631
-
648
. Registered buffer
650
applies the input signal to DRAMs
631
-
639
of semiconductor module
620
, and registered buffer
660
applies the input signal to DRAMs
640
-
648
of semiconductor module
630
.
Each of DRAMs
631
-
648
includes a test mode circuit
700
shown in FIG.
35
. Referring to
FIG. 35
, test mode circuit
700
includes P-channel MOS transistors
701
and
703
, N-channel MOS transistors
702
,
704
and
705
, an inverter
711
and an AND gate
712
.
P- and N-channel MOS transistors
701
and
702
are connected in series between a power supply node
706
and a node
710
. P- and N-channel MOS transistors
703
and
704
are connected in series between power supply node
706
and node
710
. P- and N-channel MOS transistors
703
and
704
are connected in parallel to P- and N-channel MOS transistors
701
and
702
.
P-channel MOS transistors
701
and
703
receive a voltage on power supply node
706
as a substrate voltage. A voltage on a node
708
is supplied to gate terminals of P-channel MOS transistors
701
and
703
. N-channel MOS transistor
702
receives a signal SVIH on its gate terminal, and N-channel MOS transistor
704
receives a reference voltage VDD on its gate terminal. Signal SVIH is formed of a high potential, which is input via a control pin such as an address pin in a test mode. N-channel MOS transistor
705
is connected between node
710
and a ground node
707
, and receives a control signal CSC on its gate terminal.
A differential circuit formed of P-channel MOS transistors
701
and
703
as well as N-channel MOS transistors
702
,
704
and
75
is a differential comparing circuit of a current mirror type, which becomes active in response to control signal CSC of H (logical high) level, and compares the voltage level of signal SVIH with the voltage level of reference voltage VDD for outputting a result of the comparison from a node
709
. When the voltage level of signal SVIH is higher than the voltage level of reference voltage VDD, the voltage on node
709
is lower than the voltage on node
708
, and the differential circuit outputs a signal of L (logical low) level to inverter
711
. When the voltage level of signal SVIH is lower than the voltage level of reference voltage VDD, the voltage on node
709
is higher than the voltage on node
708
so that a signal of H level is output to inverter
711
.
Inverter
711
inverts the logical level of the signal sent from node
709
, and sends it to AND gate
712
. AND gate
712
performs a logical AND on output signal of inverter
711
and control signals CSA and CSB.
For shifting DRAMs
631
-
648
to the test mode, test mode circuit
700
receives control signals CSA, CSB and CSC of H level, and also receives signal SVIH formed of a voltage level higher than the voltage level in a normal operating range. Thereby, N-channel MOS transistor
705
is turned on, and the differential circuit formed of P-channel MOS transistors
701
and
703
as well as N-channel MOS transistors
702
and
704
compares the voltage level of signal SVIH with the voltage level of reference voltage VDD, and sends the signal of L level from node
709
to inverter
711
. Inverter
711
inverts this signal of L level, and outputs the signal of H level to AND gate
712
. AND gate
712
performs a logical AND on the signal of H level sent from inverter
711
as well as control signals CSA and CSB of H level, and generates test mode signal TM of H level.
In this manner, each of DRAMs
631
-
648
is shifted to the test mode when used alone, and is subjected to various operation tests.
In the RDIMM provided with the DRAMs, however, the voltage level of the externally supplied signal is converted to the voltage level for use in the RDIMM before being output to the DRAM, as already described. Therefore, in the semiconductor module such as an RDIMM, a signal (SVIH) formed of a high voltage level shifting the DRAM to the test mode cannot be applied to the DRAMs. Consequently, the semiconductor module suffers from such a problem that the DRAM in the module cannot be shifted to the test mode.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a semiconductor memory device, which can be shifted to a test mode in a module.
Another object of the invention is to provide a semiconductor module, in which a semiconductor memory device can be shifted to a test mode.
A semiconductor memory device according to the invention includes a power supply terminal for receiving a power supply voltage; a memory cell array including a plurality of memory cells; a peripheral circuit for inputting and outputting data to and from the plurality of memory cells; and a test mode circuit for operating, in an operation of shifting to a test mode, to detect a voltage level of a power supply voltage supplied from the power supply terminal in response to external input of a test mode shift signal, and generate a test mode signal for testing a special operation when the detected voltage level is different from the voltage level in a normal operation. The peripheral circuit performs input and output of data used for testing the special operation of each of the plurality of memory cells in response to the test mode signal.
For shifting the semiconductor memory device of this invention to the test mode, the device is supplied with the power supply voltage having a voltage level different from the voltage level used in the normal operation. When the power supply voltage thus supplied is detected, the semiconductor memory device can be shifted to the test mode. According to the invention, therefore, the semiconductor memory device can be shifted to the test mode by receiving the power supply voltage with the voltage level different from the voltage level in the normal operation. Consequently, it is possible to shift the semiconductor memory device to the test mode in the semiconductor module provided with the buffer circuit, which converts the externally supplied signal to the signal formed of the voltage level used in the module.
Preferably, the test mode shift signal is formed of first and second test mode shift signals, the power supply voltage is formed of first and second power supply voltages, the test mode circuit detects the voltage level of the first power supply voltage in response to the first test mo
Hamamatsu Akihito
Tanaka Shinji
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