Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2000-09-21
2003-11-04
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
Reexamination Certificate
active
06643785
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-273218, filed Sep. 27, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to an electronic apparatus incorporating a microcomputer, such as a television receiver. More particularly, the invention relates to an interruption control circuit for restoring such an electronic apparatus from an idling state to a normal operating state.
Television receivers developed in recent years have many functions such as channel-displaying function and multi-screen displaying function. Further, they are designed to display satellite-broadcast programs and audio-multiplexed programs. To perform various functions and display programs of different types, a television receiver incorporates a microcomputer.
FIG. 6
shows a conventional microcomputer section incorporated in a television receiver. As shown in
FIG. 6
, the microcomputer section comprises a key matrix
101
, an A/D converter
105
, an input terminal
103
, a CPU (Central Processing Unit)
107
, and a ROM
109
. The input terminal
103
connects the key matrix
101
and the A/D converter
105
.
FIG. 7
shows the key matrix
101
in greater detail. The key matrix
101
has switches K
1
, K
2
, . . . , Kn and resistors R
1
, R
2
, . . . , Rn. The switches K
1
to Kn and resistors R
1
to Rk are associated with n keys (not shown), respectively. As the switches K
1
to Kn are turned on and off, in various combinations, the key matrix
101
generates different voltages.
Assume that one of the keys of the key matrix
101
is pushed. Then, the voltage assigned to the key pushed is applied from the key matrix
101
via the input terminal
103
to the A/D converter
105
. The CPU
107
drives the A/D converter
105
in accordance with the program stored in the ROM
109
. Thus driven, the A/D converter
105
converts the input voltage to digital data. The digital data is input to the CPU
107
. From the digital data the CPU
107
determines which key of the key matrix
101
has been pushed. The CPU
107
controls major components of the television receiver.
The microcomputer section shown in
FIG. 6
can accurately determine which key or keys of the key matrix
101
is pushed, no matter when it is pushed.
If the key matrix
101
remains not operated for a prescribed period of time, the television receiver is set into the idle mode. The microcomputer section always stays in the normal mode, however, no matter whether the television receiver is set in the idle mode or the normal mode. Thus, the CPU
107
keeps operating, thus causing the A/D converter
105
functioning. It is therefore determined, at regular intervals, whether the key matrix
101
has been operated or not. Since the CPU
107
keeps operating even if the television receiver stays in the idle mode, the microcomputer section consumes power at all times.
To reduce the power consumption in the microcomputer section, it has been proposed that the CPU
107
be stopped while the television receiver stays in the idle mode, thereby to turn off the A/D converter
105
. To set the CPU
107
into the normal mode from the idle mode, an interrupt signal must be supplied to the CPU
107
.
To generate an interrupt signal and supply it to the CPU
107
, the key matrix
101
must have an additional key. Moreover, the port for supplying the interrupt signal cannot serve for any other purpose.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in view of the foregoing. The object of the invention is to provide an interruption control circuit for use in an electronic apparatus incorporating a CPU. The interruption control circuit is designed to set the CPU into operation, with ease, whenever necessary, to reduce the power the apparatus consumes while the CPU remains in an idling state.
To achieve the object, the present invention provides an interruption control circuit comprising: a group of key matrices, each having keys and designed to generate different voltages when the keys are operated; an analog-to-digital converter section for converting the voltages applied from the key matrices to digital data; a control section designed to activate the analog-to-digital converter section in an normal mode, deactivate the same in an idle mode, stop operating in the idle mode, and determine, in the normal mode, which key of any key matrix has been pushed, from the digital data supplied from the analog-to-digital converter section; a plurality of buffer circuits for receiving the voltages applied from the key matrices, respectively, each buffer circuit having a threshold voltage and designed to output a first-level signal when the voltage is equal to or higher than the threshold voltage and to output a second-level signal when the voltage is lower than the threshold voltage; a logic circuit for receiving signals output from the buffer circuits and generating a detection signal when the signal output from any one of the buffer circuits changes; and an interrupt-signal generating circuit connected to the logic circuit, for generating a signal for releasing the idle mode and supplying the same to the control circuit when the logic circuit generates the detection signal.
To attain the above-mentioned object, this invention provides an interruption control circuit comprising: a group of key matrices, each having keys and designed to generate different voltages when the keys are operated; an analog-to-digital converter section for converting the voltages applied from the key matrices to digital data; a control section designed to activate the analog-to-digital converter section in an normal mode, deactivate the same in an idle mode, stop operating in the idle mode, and determine, in the normal mode, which key of any key matrix has been pushed, from the digital data supplied from the analog-to-digital converter section; a plurality of buffer circuits for receiving the voltages applied from the key matrices, respectively, each buffer circuit having a threshold voltage and designed to output a first-level signal when the voltage is equal to or higher than the threshold voltage and to output a second-level signal when the voltage is lower than the threshold voltage; a logic circuit for receiving signals output from the buffer circuits and generating a detection signal when the signal output from any one of the buffer circuits changes; an interrupt-signal generating circuit connected to the logic circuit, for generating a signal for releasing the idle mode and supplying the same to the control section when the logic circuit generates the detection signal; and a signal-supplying circuit for supplying the output signals of the buffer circuits to the control section. In this interruption control circuit, the control section selects any key matrix in which at least one key has been pushed, in accordance with the output signals of the buffer circuits, and supplies a selection signal to the analog-to-digital converter section, and the analog-to-digital converter section converts the output voltage of the key matrix to digital data.
To achieve the object described above, the present invention provides an interruption control circuit comprising: a group of key matrices, each having keys and designed to generate different voltages when the keys are operated; an analog-to-digital converter section for converting the voltages applied from the key matrices to digital data; a control section designed to deactivate the same in an idle mode, stop operating in the idle mode, and determine, in a normal mode, which key of any key matrix has been pushed, from the digital data supplied from the analog-to-digital converter section; a plurality of buffer circuits for receiving the voltages applied from the key matrices, respectively, each buffer circuit having a threshold voltage and designed to output a first-level signal when the voltage is equal to or higher than the threshold voltage and to
Kamimura Toshiyuki
Teraya Koichi
Heckler Thomas M.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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