Dram cell reading method and device

Details Dram cell reading method and device Dram cell reading method and device

2002-04-29

2003-02-04

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S149000, C365S189070, C365S203000

Reexamination Certificate

active

06515930

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to DRAMs and more specifically to a method and a device for reading a DRAM.
2. Description of the Related Art
A DRAM includes memory cells in which a logic information “1” or “0” can be stored. Each memory cell includes a capacitor in which a predetermined voltage chosen from among two values is stored according to whether a “1” or a “0” is to be stored. The capacitor of a memory cell can never be perfectly isolated and the voltage kept by the capacitor is not stable and declines along time. After a determined duration, called the retention period, the voltage stored in the capacitor of a memory cell may thus be too low to be readable. To avoid loosing the information stored in each capacitor, a refreshment of the voltage stored in each capacitor is periodically performed. For this purpose, a read device periodically compares the voltage stored in each capacitor with a reference voltage, then recharges each capacitor to one or the other of the predetermined voltages according to whether the compared voltage is greater or smaller than the reference voltage.
FIG. 1
schematically shows the structure of a conventional DRAM organized in rows and columns. Three cells M
1
, M
2
, and Mn of a same column have been shown, where n is the number of rows in the memory. Each memory cell Mi, where i ranges between 1 and n, includes a capacitor Ci having a first terminal connected to a reference voltage Vp. A second terminal of capacitor Ci is connected to a bit line BL via a switch Si. The second terminal of capacitor Ci forms an input/output terminal of memory cell Mi. The control terminal of switch Si is a selection terminal of memory cell Mi, and receives a selection signal WLi. Bit line BL is connected to an input terminal of a read device
6
via a switch
8
. Device
6
includes two identical inverters
10
and
12
assembled in antiparallel. Input I
10
of inverter
10
and the output of inverter
12
form the input terminal of device
6
. The output of inverter
10
is connected to input I
12
of inverter
12
. A high supply terminal of inverters
10
and
12
is connected to a supply voltage Vdd via a switch
14
. A low supply terminal of inverters
10
and
12
is connected to a ground voltage GND via a switch
16
. The input of inverter
12
is connected to a reference bit line BLref via a switch
18
. Reference bit line BLref is provided to have a stray capacitance identical to that of bit line BL. A reference memory cell Mref, having a structure identical to any one of memory cells Mi, is connected to reference bit line BLref. Cell Mref includes a capacitor Cref connected to bit line BLref via a switch Sref. Capacitor Cref has the same value as any one of capacitors Ci. The selection terminal of memory cell Mref receives a control signal WLref. A precharge circuit
22
, controlled by a signal PRA, is connected to terminals I
10
and I
12
. Precharge circuits, not shown, controlled by signal PRA, are connected to lines BL and BLref and to the input/output terminal of memory cell Mref. Switches
8
and
18
receive a same control signal PASS. Switch
14
receives a control signal RESTORE. Switch
16
receives a control signal SENSE. Control signals WLi, WLref, PASS, RESTORE, and PRA are generated by control means not shown.
FIG. 2
illustrates the variation along time of signals WLi and WLref, of the voltages of terminals I
10
and
112
, and of signals PASS, SENSE, RESTORE, and PRA upon refreshment of a memory cell Mi by device
6
. At an initial time t
0
, signals WLi and WLref are at 0 and capacitors Ci and Cref of memories Mi and Mref are isolated from lines BL and BLref. Signal PASS is at 0 and terminals I
10
and I
12
are isolated from lines BL and BLref. Signals SENSE and RESTORE are at 0 and inverters
10
and
12
are deactivated. Signal PRA is at 1 and block
22
forces the voltages of terminals I
10
and I
12
to a voltage Vdd/2. Similarly, precharge circuits, not shown, force bit lines BL and BLref to voltage Vdd/2, and the input/output terminal of cell Mref to a reference voltage, which is considered, for simplification, to be equal to Vdd/2. At a time t
1
, signal PRA is brought to 0. The precharge circuits are then deactivated. At a time t
2
, signals WLi, WLref and PASS are brought to 1. Capacitors Ci and Cref are then respectively connected to terminals
110
and
112
. Bit line BL and terminal I
10
each exhibit a predetermined impedance, mainly capacitive. From time t
2
, the charges stored in capacitor Ci distribute between capacitor Ci and the stray capacitances of line BL and of terminal I
10
.
FIG. 2
illustrates an example in which a positive voltage Vdd/2+&Dgr;V is stored in capacitor Ci before time t
2
. After time t
2
, the charges which were stored in capacitor Ci distribute between capacitor Ci and the stray capacitances of line BL and of terminal I
10
. Terminal I
10
is thus brought to a voltage Vdd/2+&dgr;V smaller than voltage Vdd/2+&Dgr;V. Terminal I
12
, connected to line BLref and to capacitor Cref, remains at voltage Vdd/2. At a time t
3
, signal SENSE is brought to 1 to turn switch
16
on. The low supply terminals of inverters
10
and
12
are then connected to voltage GND. As a response to voltage Vdd/2+&dgr;V of terminal I
10
, inverter
10
forces terminal I
12
and line BLref to voltage GND. At a time t
4
, signal RESTORE is brought to 1 to turn switch
14
on. Inverters
10
and
12
are then supplied by voltage Vdd, and inverter
12
forces terminal I
10
and line BL to voltage Vdd. Capacitor Ci is then recharged by inverter
12
, and the operation of refreshing cell Mi is over. At a time t
5
, control signals WLi and WLref are brought to 0 to isolate capacitors Ci and Cref from bit lines BL and BLref. At a time t
6
, signals SENSE and RESTORE are brought to 0 to turn switches
14
and
16
off and deactivate inverters
10
and
12
. At a time t
7
, signal PASS is brought to 0, to turn off switches
8
and
18
and to isolate terminals I
10
and I
12
from lines BL and BLref. At a time t
7
, signal PRA is brought to 1 to control the precharge of terminals I
10
and I
12
, of lines BL and BLref, and of capacitor Cref, to prepare a next refreshment operation.
A read operation in memory Mi is identical to the refreshment operation just described. The result of the read operation is for example indicated by the state of terminal I
10
at time t
5
. A write operation into cell Mi, in which a means not shown forces the state of terminal I
10
whatever the voltage stored in capacitor Ci, is not described herein.
If voltage Vdd/2+&dgr;V provided at the input terminal of device
6
in a refreshment or read operation is insufficient to control it, said device cannot operate satisfactorily. Voltage Vdd/2+&dgr;V depends on voltage Vdd/2+&Dgr;V stored in capacitor Ci of the memory cell, and on the ratio between capacitor Ci and the stray capacitances of the bit line and of the input terminal of device
6
.
Technological progress and the more and more advanced integration of memory circuits cause a reduction in the size of capacitors Ci and in supply voltage Vdd. A first consequence is that the voltages stored in the memory cells are smaller and smaller. A second consequence is that the memory cell capacitors have lower and lower values as compared to the stray capacitances of the bit line and of the read device input terminal. As a result, the potential difference &dgr;V to be detected in a reading decreases. Indeed, the stray capacitance of the bit line, which depends on the length and on the surface area of the bit line, is difficult to reduce. The stray capacitance of the input terminal of device
6
especially depends on the size of the gates of the transistors forming inverters
10
and
12
. Now, inverters
10
and
12
have a high output impedance to be able to control the memory cell charge via the bit lines. Inverters
10
and
12
are thus formed of large transistors having a high gate capacitance and the stray capac

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