Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-19
2003-10-28
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S386000
Reexamination Certificate
active
06639288
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device such as a MOS (Metal Oxide Semiconductor) capacitor, a MOS transistor and a semiconductor integrated circuit, and more particularly to a method of manufacturing a semiconductor device in which a conductor is formed on an insulating film.
2. Description of the Background Art
As an example of background-art semiconductor device, a MOS capacitor, a MOS transistor and a semiconductor integrated circuit will be taken for the following discussion. In the MOS capacitor and the MOS transistor, an electrode on a gate insulating film corresponds to a conductor formed on an insulating film. In the semiconductor integrated circuit, a wire on an interlayer insulating film corresponds to the conductor formed on the insulating film.
FIG. 61
is a schematic diagram showing an example of sectional structure of a background-art MOS capacitor. In the MOS capacitor of
FIG. 61
, a gate insulating film
202
is provided on an N-type impurity diffusion layer
201
b
existing on one of major surfaces of a semiconductor substrate
201
a
. On the gate insulating film
202
, a polysilicon
203
doped with boron and a tungsten silicide
204
are layered in this order, constituting a gate electrode. On the tungsten silicide
204
, an insulating film
205
is formed. Arrows
206
of
FIG. 61
indicate that the boron in the polysilicon
203
reaches the N-type impurity diffusion layer
201
b
through the gate insulating film
202
. Such a phenomenon as the boron in the polysilicon
203
goes through the gate insulating film
202
is caused by thermal diffusion of the boron in the gate insulating film
202
, resulting from a heat treatment for electrically activating a dopant in the semiconductor substrate
201
b
. That results in disadvantageous variation of threshold voltage of the MOS structure. Further, the boron in the polysilicon
203
is sucked from the polysilicon
203
out into the tungsten silicide (WSix)
204
as indicated by arrows
207
during the above heat treatment. The character x of WSix represents composition ratio, usually taking a value in a range from 2 to 3.
When the temperature of the boron in the polysilicon
203
falls due to movement of the boron such as going through the gate insulating film
202
and being sucked out into the tungsten silicide
204
, the polysilicon
203
is depleted in application of negative voltage with reference to the semiconductor substrate
201
a
to the tungsten silicide
204
. With depletion of the polysilicon
203
, gate capacitance decreases, as shown in
FIG. 62
, in a region in which a channel is to be inverted, i.e., a region to which a negative voltage is applied.
The same occurs in the MOS transistor as does in the MOS capacitor.
FIG. 63
shows a sectional structure of a background-art MOS transistor which is a constituent of a memory cell of a DRAM. The structure of the MOS transistor of
FIG. 63
will be first discussed. The MOS transistor of
FIG. 63
is isolated from other elements (not shown) on a semiconductor
1
a
by a shallow trench isolation
20
formed of a silicon oxide film on one of major surfaces of the semiconductor substrate
1
a
. Hereinafter, the shallow trench isolation is referred to as STI. In the one major surface of the semiconductor substrate
1
a
surrounded by the STI
20
, an N-type source/drain region
13
is formed, to be connected to a storage capacitor (not shown). In the one major surface of the semiconductor substrate
1
a
surrounded by the STI
20
, an N-type source/drain region
14
is so formed as not to come into contact with the N-type source/drain region
13
. The N-type source/drain region
14
is connected to a bit line (not shown). A region between the N-type source/drain regions
13
and
14
is defined as a channel region, and a gate insulating film
2
is formed on the channel region in the one major surface of the semiconductor substrate
1
a
. On the gate insulating film
2
, a doped polysilicon
18
is formed in a layered manner, and a tungsten silicide
19
is formed in a layered manner thereon. The doped polysilicon
18
and the tungsten silicide
19
constitute a gate electrode. Further, on the one major surface of the semiconductor substrate
1
a
, a nitrided oxide film
10
a
is so formed as to cover the gate insulating film
2
and the gate electrode, and an insulating film
10
b
having a thickness of about 50 nm is formed thereon.
For the same reason as in the MOS capacitor, when the doped polysilicon
18
is depleted and the gate capacitance decreases, a drain current decreases in the MOS transistor, causing deterioration of circuit performance. For example, Japanese Patent Application Laid Open Gazette No. 5-243564 discloses a MOS transistor consisting of tungsten side walls and a polysilicon doped with phosphorus for control of threshold voltage, and this structure also has the problem of depletion of the gate electrode.
As a method of solving the above problem of gate depletion proposed is use of a metal gate electrode.
FIG. 64
shows an example of structure of a MOS capacitor using a metal gate electrode. In the MOS capacitor of
FIG. 64
, a tungsten
209
is used instead of the polysilicon
203
and the tungsten silicide
204
of FIG.
61
. The tungsten
209
is formed on the gate insulating film
202
with a thin tungsten nitride
208
(WNx) interposed therebetween. The tungsten nitride
208
is placed below the tungsten
209
in order to prevent diffusion of tungsten atoms into the gate insulating film
202
to form fixed charges. If the fixed charges are formed, the threshold voltage of the transistor disadvantageously varies more widely than expected in a designing stage. Further, in order to prevent diffusion of tungsten atoms into other regions, the insulating film
205
is provided on the tungsten
209
. In the structure of the MOS capacitor of
FIG. 64
, no depletion of the gate electrode occurs. Therefore, no decrease of drain current due to the gate depletion occurs.
Having the above structure, even when the metal nitride such as a tungsten nitride is sandwiched between the metal gate electrode and the gate insulating film, the background semiconductor device has a problem that poor cohesiveness between the metal gate electrode such as tungsten and the gate insulating film makes the metal gate electrode easy to remove. The problem becomes more serious as the semiconductor device becomes smaller since an area of contact between the gate insulating film
202
and the tungsten
209
becomes smaller as the gate length
210
or the gate width becomes smaller.
The problem that the metal gate electrode is easy to remove arises not only in the case where the tungsten is used as the gate electrode but also in the case where the metal is used as the bit line of the DRAM. For example,
FIG. 65
shows a sectional structure of a region where the memory cell of the DRAM is formed when cut by one section parallel to a word line and in this figure, a bit line
219
formed of metal such as tungsten is disadvantageously easy to remove.
Now, a structure of the DRAM shown in
FIG. 65
will be discussed. On the one major surface of the semiconductor substrate
1
a
, the STI
20
is formed, isolating the MOS transistor whose one of constituents is an N-type impurity diffusion layer
220
. Entirely on the semiconductor substrate
1
a
having this structure, an interlayer insulating film
212
is formed, and a nitride film
213
is formed further thereon. A storage node
215
is formed on the nitride film
213
and inside a through hole which penetrates the nitride film
213
and the interlayer insulating film
212
to reach the N-type impurity diffusion layer
220
. A dielectric
216
is sandwiched between the storage node
215
and a cell plate
217
corresponding to the storage node
215
. An interlayer insulating film
214
is so formed on the nitride film
213
as to cover the storage node
215
and the cell plate
217
. On the interlayer insulating film
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Cuong Quang
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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