Electrical computers and digital data processing systems: input/ – Input/output data processing
Reexamination Certificate
2000-08-07
2003-12-02
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
C710S033000, C710S052000, C710S106000, C712S225000
Reexamination Certificate
active
06658493
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer with a transmission/reception buffer in which a data transmission to a host computer and a data reception from the host computer are performed, and more particularly to a microcomputer in which various problems occurring in a data exchange with the host computer are solved.
2. Description of Related Art
FIG. 12
is a block diagram showing the configuration of a conventional system composed of a conventional microcomputer and a host computer connected with the conventional microcomputer. In
FIG. 12
, a reference sign
25
indicates a microcomputer, a reference sign
26
indicates a host computer, a reference sign
27
indicates a central processing unit, a reference sign
28
indicates a read only memory (ROM), a reference sign
29
indicates a random access memory (RAM), a reference sign
30
indicates an enciphering circuit for performing a data enciphering processing and a data deciphering processing, a reference sign
31
indicates an integrated circuit (IC) card interface circuit for exchanging data with an IC card, a reference sign
32
indicates a re-writable ROM for storing various types of data, a reference sign
33
indicates a direct memory access controller (DMAC), a reference sign
34
indicates a host interface circuit for receiving and transmitting data from/to the host computer
26
, and a reference sign
35
indicates an internal data bus having an 8-bit bus width. In this prior art, as information received and transmitted between the host computer
26
and the host interface circuit
34
, data passing through an external data bus having an 8-bit bus width, a pair of an external read control signal and an external write signal (R/W), an external chip selection (CS) signal and other various control signals are shown in FIG.
12
.
FIG. 13
is a block diagram showing the configuration of the host interface circuit
34
of the conventional microcomputer and a periphery of the host interface circuit
34
. In
FIG. 13
, a reference sign
36
indicates a transmission/reception buffer arranged between the external data bus and the internal data bus
35
, a reference sign
37
indicates a reception flag, a reference sign
38
indicates a transmission flag for outputting a read-out signal, and a reference sign
39
indicates a ready flag for outputting a busy signal.
Next, an operation will be described.
FIG. 14
is a flow chart showing the procedure performed in the conventional system shown in FIG.
12
and
FIG. 13
according to a program executed in the central processing unit
27
in cases where data is written in the transmission/reception buffer
36
. In
FIG. 14
, in a data transmission from the host computer
26
to the microcomputer
25
functioning as a slave processor, an operation of the host interface circuit
34
is started to prepare the holding of the reception data in the transmission/reception buffer
36
. Thereafter, in a step ST
15
, it is judged by referring to a value of the reception flag
37
whether or not reception data not yet read-out exists in the transmission/reception buffer
36
. In cases where reception data not yet read-out exists, in a step ST
16
, the central processing unit
27
accesses to the transmission/reception buffer
36
to read out the reception data not yet read-out. Thereafter, in a step ST
17
, it is judged by referring to a value of the reception flag
37
whether or not next reception data is received in the transmission/reception buffer
36
. In cases where next reception data is received from the host computer
26
, the procedure returns to the step ST
15
. In contrast, in cases where next reception data is not received, the procedure is completed.
FIG. 15
is a flow chart showing the procedure performed in the conventional system shown in FIG.
12
and
FIG. 13
according to a program executed in the central processing unit
27
in cases where data to be transmitted to the host computer
26
is generated in the central processing unit
27
. In
FIG. 15
, in a data transmission from the microcomputer
25
functioning as a slave processor to the host computer
26
, an operation of the host interface circuit
34
is started to prepare the writing of transmission data generated in the central processing unit
27
in the transmission/reception buffer
36
. Thereafter, in a step ST
18
, it is judged by referring to the transmission flag
38
whether or not transmission data to be transmitted to the host computer
26
exists in the transmission/reception buffer
36
. In cases where preceding transmission data to be transmitted to the host computer
26
exists in the transmission/reception buffer
36
, the procedure waits for the reading-out of the preceding transmission data from the transmission/reception buffer
36
. In contrast, in cases where preceding transmission data to be transmitted to the host computer
26
does not exist, in a step ST
19
, the central processing unit
27
accesses to the transmission/reception buffer
36
to write current transmission data generated in the central processing unit
27
in the transmission/reception buffer
36
. Thereafter, it is judged by referring to the transmission flag
38
whether or not next transmission data to be transmitted to the host computer
26
is generated in the central processing unit
27
. In cases where next transmission data is generated in the central processing unit
27
, the procedure returns to the step ST
18
. In contrast, in cases where next transmission data is not generated in the central processing unit
27
, the procedure is completed.
As is described above, in cases where the data transmission/reception is performed between the host computer
26
and the microcomputer
25
, a handshaking described hereinafter in detail is established between the host computer
26
and the microcomputer
25
under the control of the central processing unit
27
.
For example, in cases where data is transmitted from the host computer
26
to the microcomputer
25
, the host computer
26
sets data on the external data bus, asserts an external chip selection signal set to a low level and drives an external read/write signal to a low level. In response to the signal setting of the host computer
26
, in the microcomputer
25
, the transmission/reception buffer
36
latches and holds the data transmitted through the external data bus in synchronization with an edge of the external write control signal, a flag is set in the reception flag
37
to inhibit another data holding of the transmission/reception buffer
36
. Thereafter, the procedure shown in
FIG. 14
is performed according to the flag of the reception flag
37
under the control of the central processing unit
27
to read out the data held in the transmission/reception buffer
36
and to perform the prescribed processing. For example, in cases where enciphered data is received in the microcomputer
25
, the enciphered data is transferred from the transmission/reception buffer
36
to an enciphered data buffer of the enciphering circuit
30
to decipher the enciphered data in the enciphering circuit
30
, and various operations are performed according to the deciphered data.
Also, in cases where data is transmitted from the microcomputer
25
to the host computer
26
, the microcomputer
25
holds the data in the transmission/reception buffer
36
. In response to the data holding, a flag is set in each of the transmission flag
38
and the ready flag
39
to inhibit another data holding of the transmission/reception buffer
36
. Thereafter, the host computer
26
reads out the data from the transmission/reception buffer
36
according to the states of the transmission flag
38
and the ready flag
39
.
After the data read-out, each of the reception flag
37
, the transmission flag
38
and the ready flag
39
is reset by a hardware operation of the microcomputer
25
according to an access to the transmission/reception buffer
36
or a data holding state of the transmission/reception buffer
36
.
Because the co
Burns Doane , Swecker, Mathis LLP
Gaffin Jeffrey
Mitsubishi Denki & Kabushiki Kaisha
RiJue Mai
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