Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer
Reexamination Certificate
2001-11-30
2003-06-10
Hu, Shouxiang (Department: 2811)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
On insulating substrate or layer
C438S341000, C438S478000
Reexamination Certificate
active
06576532
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to techniques for making semiconductor devices and more particularly to forming heteroepitaxial structures.
2. Related Art
There are a variety of uses in semiconductor manufacturing for heteroepitaxial structures, structures in which one type of semiconductor material is grown on the top of another type. The desire is for both the underlying semiconductor material and the overlying semiconductor material to be monocrystalline. The difficulty in this is that often the desired overlying semiconductor material has a mismatch in its crystalline structure with that of the underlying crystalline material. The problem can occur for any situation in which there are two types of semiconductor materials desired for a particular integrated circuit, but currently a typical case is for the underlying semiconductor material to be silicon because that is the most common for making integrated circuits. In the case of optical electronics, it is desirable to use germanium, which is an excellent material for use as a photodetector because of its relatively low band gap. Thus, with silicon being desirable for its use in making transistors for circuits, it would be beneficial to have a germanium layer as well as a silicon layer so that a photodetector useful for near infrared communications wavelengths (1300-1550 nanometers) can be combined with transistor circuitry on the same integrated circuit.
Germanium and silicon, however, have crystalline structures that have a 4 percent mismatch in the lattice constant. The result of epitaxially growing a germanium layer over the silicon substrate is the formation of misfit dislocations. The misfit dislocations in turn cause threading dislocations. The threading dislocations create major problems with leakage and efficiency reduction of the photodetector. Whereas misfit dislocations remain near and parallel to the underlying substrate, threading dislocations propagate through the entire thickness of the epitaxially-grown overlying layer.
One of the techniques that has been used to reduce the number of threading dislocations in the overlying germanium layer is to introduce an intermediate graded buffer layer between the silicon substrate and the germanium layer. The graded buffer is comprised of silicon and germanium with a local composition that can be described as Si
1−x
Ge
x
. During the growth of the graded buffer layer the composition starts at x=0 and gradually increases with increasing film thickness until x=1 is achieved. The change in x can either be continuous or it can be accomplished in a stepwise fashion. Following deposition of the graded buffer layer, the desired germanium layer is deposited on top of the buffer layer. This technique has been demonstrated to be able to confine a majority of the threading dislocations in the buffer layer and hence to achieve a substantial decrease in the threading dislocations in the overlying germanium layer. A disadvantage of this technique is that a thick buffer layer is required to achieve the desired decrease in threading dislocations in the overlying germanium layer. Typically the graded buffer layer needs to be approximately 10 microns thick or greater. This results in a long and expensive deposition. Additionally, the great difference in height of the silicon surface and the germanium surface will result in integration difficulties if an integrated circuit is to be fabricated from devices fabricated in the silicon surface and photodetectors in the germanium surface. Because of the disadvantages of the graded buffer technique, there have been efforts to develop alternate techniques that reduce the threading dislocations in the overlying germanium layer but with substantial reduction in thickness of any intermediate layer.
One such technique is to provide high heat to the germanium to heal the threading dislocations. Thermal cycling to a temperature of approximately 900 degrees Celsius or above is used to cause the threading dislocations to glide. Threading dislocations can be removed from the film either by gliding to the edge of the sample or by two threading dislocations gliding together and annihilating. Longer anneal times at 900 degrees Celsius or an increased number of thermal cycles to 900 degrees Celsius have been found to reduce the density of remaining threading dislocations. Additionally, this technique has been used with mesas of germanium with restricted lateral dimensions of typically 10 to 20 microns. The germanium mesas are formed by selective growth of germanium in windows opened in a dielectric layer to expose underlying silicon. The selective germanium deposition nucleates and grows on the exposed silicon surface but not on the dielectric layer. The germanium mesas lie within the opening in the dielectric window. During the post-deposition thermal cycling, which occurs at high temperature, the restricted size of a mesa assists the gliding of threading dislocation to the dielectric layer at the edge of the mesa. This technique has been demonstrated to be beneficial in reducing threading dislocation densities, however the best reported results are not yet as good as those achieved with the graded buffer layer. The thermal cycling technique does have the advantage of achieving a reduced threading dislocation density in a thin layer of germanium. The use of multiple, high temperature thermal cycles, however, adversely affects any transistors that have already been formed in the integrated circuit. The transistors are formed with a certain amount of total heat energy that is a combination of time and temperature. This is generally known as a thermal budget. Thus, the transistors formed in the silicon portion of the integrated circuit, prior to formation of the germanium layer, have substantially used up the available thermal budget. Additional heating steps must be kept at relatively low temperature such as below 600 degrees Celsius or at least for the cases where that temperature is exceeded, it is exceeded for short time periods.
Another technique for growth of germanium on a silicon substrate is epitaxial lateral overgrowth. In this technique, the silicon substrate is covered with an amorphous dielectric layer, (such as silicon oxide or silicon nitride), and then a pattern of openings in the dielectric layer to the underlying silicon is created using lithographic patterning processes. Selective epitaxial germanium deposition nucleates and grows over the exposed silicon regions. In the present process, however, the epitaxial germanium deposition is continued until the germanium overfills the opening in the dielectric and begins to overgrow the upper surface of the dielectric layer. The growth process is continued until the germanium material from adjacent opening meets and a continuous film is formed across the substrate. The germanium grown over the upper surface of the amorphous dielectric layer is free to assume the natural germanium lattice constant. Threading dislocations can still occur in the germanium grown directly over the silicon nucleation regions. Thermal cycling as discussed above could be used to glide the threading dislocations to the sides of the openings in the dielectric layer. Alternatively, since the threading dislocations form at 45 degrees to the silicon surface for germanium grown on (100) silicon, if the height of the opening is greater than the diameter of the opening, then the threading dislocations will terminate on the perimeter of the opening. Another aspect of epitaxial lateral overgrowth is that a seam can occur where the germanium from two adjacent nucleation sites merge. The germanium layers grown with this technique, however, can result in no defects at many seams and in twins or low angle grain boundaries at other seams that have minimal impact on the electrical properties. A disadvantage of this technique is that a thicker germanium layer must be deposited to first fill the holes and then to form the desired layer. Additionally, if the holes and spaces ar
Jones Robert E.
White Bruce E.
Chiu Joanna G.
Clingan, Jr. James L.
Hu Shouxiang
Motorola Inc.
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