Semiconductor memory device having internal circuit...

Details Semiconductor memory device having internal circuit... Semiconductor memory device having internal circuit...

2002-08-13

2003-11-25

Phung, Anh (Department: 2819)

Static information storage and retrieval

Read/write circuit

Testing

C365S226000, C365S189050

Reexamination Certificate

active

06654300

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly relates to an internal voltage generation circuit capable of adjusting internal voltage during a test.
2. Description of the Background Art
Generally, periods in which failures occur to a semiconductor memory device are roughly divided into three periods, which periods are also referred to as a an initial failure period, a chance failure period and a wear-out failure period in the order of time.
In the initial failure period, a defect at the time of the manufacture of a semiconductor memory device appears as a failure. The initial failure period is a period in which an initial failure occurs right after starting the use of the semiconductor. The rate of this initial failure sharply decreases with the passage of time. The initial failure period is followed by the chance failure period in which a low failure rate continuous for a certain period of time. With time, the life of the semiconductor memory device nears the useful life thereof and the semiconductor memory device enters the wear-out failure period in which the failure rate suddenly increases. If the operation reliability of the semiconductor memory device while being in use is considered, it is necessary to use the semiconductor memory device within the chance failure period. Namely, it is necessary to remove semiconductor memories to which initial failures occur before shipment. To this end, semiconductor memories are subjected to accelerated operation aging for a certain period of time and to screening for removing defects having initial failures.
To perform efficient screening, it is necessary to discover an initial failure in short time. Generally, a screening method for raising internal voltage which is used as operating power supply voltage in semiconductor memory device from voltage in normal operation, applying high field stress to the memory and thereby screening semiconductor memories is used.
FIG. 8
is a conceptual view of a conventional internal voltage generation circuit
20
which generates internal voltage applied to the internal circuit of a semiconductor memory device.
Referring to
FIG. 8
, internal voltage generation circuit
20
includes reference voltage generation circuits
300
a
to
300
c
which generate reference voltages REF
1
to REF
3
, respectively, and internal voltage generation units
400
a
to
400
c
which receive corresponding to reference voltages REF
1
to REF
3
, and generate internal voltages V
1
to V
3
respectively.
FIG. 9
is a circuit block diagram of reference voltage generation circuit
300
a
generating reference voltage REF
1
. Since reference voltage generation circuits
300
a
to
300
c
are equal in configuration, the configuration of reference voltage generation circuit
300
a
will be typically explained herein.
Referring to
FIG. 9
, reference voltage generation circuit
300
a
includes a current mirror amplifier
310
, a starting circuit
320
which operates at startup, a constant current circuit
330
which generates a constant current, a tuning circuit
340
and a reference voltage setting circuit
350
.
Reference voltage setting circuit
350
sets the voltage level of an internal node to be described later. Current mirror amplifier
310
generates a reference voltage in accordance with the voltage level of this internal node. Tuning circuit
340
and constant current circuit
330
are used to adjust the voltage level of the internal node. Constant current circuit
330
supplies a constant current to reference voltage setting circuit
350
, and tuning circuit
340
adjusts a resistance element to be described later and tunes the voltage level of the internal node. Starting circuit
320
indicates the activation of constant current circuit
330
when the power of the semiconductor memory device is turned on.
Current mirror amplifier
310
includes P-channel MOS transistors
311
and
312
, and N-channel MOS transistors
313
to
315
. P-channel MOS transistor
311
and N-channel MOS transistor
313
are connected in series between a power supply voltage VCC and a node N
1
through a node N
2
and the gates of P-channel MOS transistors
311
and N-channel MOS transistor
313
are connected to node N
2
and an internal node N
6
, respectively. P-channel MOS transistor
312
and N-channel MOS transistor
314
are connected in series between power supply voltage VCC and node N
1
through a node N
0
and the gates of P-channel MOS transistors
312
and N-channel MOS transistor
314
are connected to node N
2
and node N
0
, respectively. Further, N-channel MOS transistor
315
is connected between node N
1
and a ground voltage GND and the gate thereof is connected to a node N
4
.
By such a current mirror structure, current mirror amplifier
310
sets reference voltage REF
1
generated at node N
0
at the voltage level of voltage Vn
6
of internal node N
6
connected to the gate of N-channel MOS transistor
313
.
Starting circuit
320
includes a P-channel MOS transistor
321
and an N-channel MOS transistor
322
.
P-channel MOS transistors
321
and N-channel MOS transistor
322
are connected between power supply voltage VCC and ground voltage GND through a node N
3
and the gates of P-channel MOS transistors
321
and N-channel MOS transistor
322
are connected to ground voltage GND and a node N
4
, respectively.
At startup, starting circuit
320
raises the voltage level of node N
3
in response to the rise of power supply voltage VCC. Following this, an N-channel MOS transistor
323
which is provided in constant current circuit
330
becomes conductive, nodes N
4
and N
5
are electrically connected to each other and constant current circuit
330
is activated. It is noted that starting circuit
320
turns N-channel MOS transistor
323
into a nonconductive state after the passage of a predetermined period. This is because the voltage level of node N
3
decreases if N-channel MOS transistor
322
is conductive.
Constant current circuit
330
includes a resistance
332
, P-channel MOS transistors
331
and
333
, and N-channel MOS transistors
323
,
334
and
335
.
P-channel MOS transistors
331
and N-channel MOS transistor
334
are connected in series between power supply voltage VCC and ground voltage GND through node N
5
and the gates of P-channel MOS transistors
331
and N-channel MOS transistor
334
are connected to nodes N
5
and N
4
, respectively. Resistance
332
, P-channel MOS transistors
333
and N-channel MOS transistor
335
are connected in series between power supply voltage VCC and ground voltage GND through node N
4
and the gates of P-channel MOS transistors
333
and N-channel MOS transistor
335
are connected to nodes N
5
and N
4
, respectively.
N-channel MOS transistor
323
is connected between nodes N
4
and N
5
and the gate thereof is connected to node N
3
. N-channel MOS transistors
334
and
335
constitute a current mirror circuit. If N-channel MOS transistors
334
and
335
have high channel resistances, the same current is carried to P-channel MOS transistors
331
and
333
by N-channel MOS transistors
334
and
335
which constitute a current mirror circuit.
Reference voltage setting circuit
350
includes P-channel MOS transistors
302
and
351
to
361
, and an inverter
362
.
P-channel MOS transistor
302
is connected between power supply voltage VCC and internal node N
6
and the gate thereof is connected to node N
5
. P-channel MOS transistors
351
to
357
are connected in series between internal node N
6
and ground voltage GND and the gates thereof are connected to ground voltage GND. P-channel MOS transistors
358
to
361
are provided as transistor switches so as to short-circuit P-channel MOS transistors
352
to
355
, respectively (which P-channel MOS transistors
358
to
361
will be also referred to as “transistor switches” hereinafter), and the gates thereof receive the input of tuning circuit
340
. The gate of P-channel MOS transistor
361
receives a signal input

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