Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-11
2003-12-23
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S392000, C257S395000, C257S397000, C257S295000
Reexamination Certificate
active
06667524
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device provided with a plurality of semiconductor elements, and more particularly to a semiconductor device provided with a plurality of semiconductor elements having different threshold voltages.
2. Description of the Background Art
In a semiconductor device provided with a plurality of semiconductor elements, there are cases where semiconductor elements having their threshold voltages (Vth) set different from one another are required.
A first case where such semiconductor elements having different threshold voltages (Vth) are required is as follows. In recent years, semiconductor devices having lower threshold voltages have been desired, because of increasing demands for reduction of power consumption, widening of applications of handheld equipment, securing of device reliability, and thus, the devices need to operate at low voltages (of not greater than 1 V, for example). Reduction of the threshold voltage, however, leads to an increase of sub-threshold leakage in a semiconductor element. To solve the problem, Nippon Telegraph and Telephone Corporation has developed a MT (Multi)-CMOS (Complementary Metal Oxide Semiconductor) circuit.
In a second case, semiconductor elements having different threshold voltages (Vth) are required to restrict occurrence of channel leakage in a narrow channel width transistor. In a semiconductor device having a logic circuit with an SRAM (Static Random Access Memory) built therein, it is common to make the channel width (W
1
) of a transistor constituting the SRAM portion narrower than the channel width (W
2
) of a transistor constituting a peripheral logic circuit system, to limit the area dedicated to the SRAM portion.
When a transistor having such a narrow channel width is employed, however, channel leakage increases more in the SRAM portion than in the peripheral logic circuit, specifically in a p channel transistor (Vth_typ), and especially in a low-threshold voltage (Vth) transistor (Vth_L), as shown in FIG.
19
. This is presumably because the low threshold voltage of the narrow channel width transistor is decreased due to stress from an isolation insulating film region or the like.
FIG. 19
schematically shows a relation of Vg (gate voltage)—Id (drain current) of a p channel transistor. Channel leakage corresponds to a sub-threshold leakage value |log Ids| when Vg=0, as shown as Ioff in FIG.
19
. As shown in
FIG. 20
, the channel leakage tends to increase in the narrow channel width transistor with a lower threshold voltage condition.
As described above, in a transistor used in a semiconductor device, threshold voltage setting is changed by changing dopant impurity concentration of a channel region. To change the impurity concentration of the channel region, it is necessary to cover with a resist mask a region other than a transistor forming region of a transistor having a threshold voltage to be changed, and to introduce a dopant impurity into the transistor forming region to change the threshold voltage. With this method, however, the number of manufacturing steps, WP TAT (Wafer Process Turn Around Time), and manufacturing cost of the semiconductor device will all increase.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having semiconductor elements of different threshold voltages, without increasing the number of manufacturing steps and others.
According to an aspect of the semiconductor device based on the present invention, the semiconductor device is provided with a first semiconductor element and a second semiconductor element of the same channel type as the first semiconductor element. The first semiconductor element includes: a first active region provided in a semiconductor substrate; a first gate electrode provided on the first active region with a first gate insulating film interposed therebetween; a pair of first impurity diffusion regions having the same conductivity type as the first active region and provided in the first active region to sandwich the first gate electrode; second impurity diffusion regions having the same conductivity type as the first impurity diffusion regions and each provided in respective one of the first impurity diffusion regions in a region shallower than a diffusion depth of the first impurity diffusion region; third impurity diffusion regions having a different conductivity type from the second impurity diffusion regions and each provided in respective one of the second impurity diffusion regions in a region shallower than a diffusion depth of the second impurity diffusion region; and fourth impurity diffusion regions having the same conductivity type as the third impurity diffusion regions and each provided in respective one of the third impurity diffusion regions in a region shallower than a diffusion depth of the third impurity diffusion region.
The second semiconductor element includes: a second active region having the same conductivity type as the first active region and provided in the semiconductor substrate; a second gate electrode provided on the second active region with a second gate insulating film interposed therebetween; a pair of fifth impurity diffusion regions corresponding to the first impurity diffusion regions and having the same conductivity type as the first impurity diffusion regions; sixth impurity diffusion regions corresponding to the third impurity diffusion regions and having the same conductivity type as the third impurity diffusion regions; and seventh impurity diffusion regions corresponding to the fourth impurity diffusion regions and having the same conductivity type as the fourth impurity diffusion regions.
Further, the first semiconductor element constitutes a transistor for use in a memory cell region, and the second semiconductor element constitutes a transistor for use in a peripheral circuit region. A first total impurity concentration of the first impurity diffusion region and the second impurity diffusion region in the first semiconductor element is set higher than a second total impurity concentration of the fifth impurity diffusion region in the second semiconductor element.
With this configuration, the first total impurity concentration constituting, e.g., an SPI (Shallow Pocket Implant) region of the first semiconductor element is set higher than the second total impurity concentration constituting, e.g., the SPI region of the second semiconductor element. Thus, it is possible to restrict channel leakage in the first semiconductor element used in the memory cell region to the same degree as in the second semiconductor element.
According to another aspect of the semiconductor device based on the present invention, the semiconductor device is provided with a first semiconductor element and a second semiconductor element of the same channel type as the first semiconductor element. The first semiconductor element includes: a first active region provided in a semiconductor substrate; a first gate electrode provided on the first active region with a first gate insulating film interposed therebetween; a pair of first impurity diffusion regions having the same conductivity type as the first active region and provided in the first active region to sandwich the first gate electrode; second impurity diffusion regions having the same conductivity type as the first impurity diffusion regions and each provided in respective one of the first impurity diffusion regions in a region shallower than a diffusion depth of the first impurity diffusion region; third impurity diffusion regions having a different conductivity type from the second impurity diffusion regions and each provided in respective one of the second impurity diffusion regions in a region shallower than a diffusion depth of the second impurity diffusion region; and fourth impurity diffusion regions having the same conductivity type as the third impurity diffusion regions and each provided in respective one of the third impurity d
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Wojciechowicz Edward
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