Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-22
2003-11-04
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C327S108000, C327S111000
Reexamination Certificate
active
06642578
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to depletion mode field effect transistors. More specifically, the invention relates to a high power transistor suitable for use as a radio frequency switch in wireless telephony applications.
BACKGROUND OF THE INVENTION
Field effect transistors (FETs) are semiconductor devices that are used in a variety of switching applications. For example, in radio frequency applications, one can connect FETs in a series-shunt combination to provide a single pole, double throw (SPDT) switch. Cellular telephones use such a switch to alternately connect the radio transmitter or receiver portion of the phone to the antenna. In such a switch, four FETs are used. Two act as series connected devices, one to connect either the receiver or transmitter to the antenna and the other to isolate the transmitter or receiver from the antenna. The other two FETs are used to shunt undesired signals from the isolated receiver or transmitter to ground.
A FET typically has three electrical terminals: a source, a drain, and a gate. When a FET is used as a switch, the switch input is the drain and the switch output is the source, or vice-versa. The switched signal passes through a conductive region, called the channel. In a depletion mode FET (i.e., a FET that is normally on), a control voltage is applied to the gate (or between the gate and the source) to turn the device off. The level of voltage sufficient to turn the device off is known as the pinch-off voltage (V
po
). When the pinch-off voltage is applied to the gate, the free carriers of electrical current are depleted in the channel region, rendering the semiconductor material in the channel non-conductive. A channel in this condition prevents signal current from passing between the source and drain terminals. The free carriers in the channel can also be depleted by an excessive amount of signal current. This type of depletion is known as saturation. Saturation occurs gradually along the length of the channel. The zero voltage (present at the gate) saturation current is known as I
dss
. In any-given channel, if its length, i.e., the distance between the source and drain terminals, is decreased, then the I
dss
for the transistor increases.
In order to increase the current carrying capacity of the entire FET, several channels may be formed between the interdigitated fingers of alternating source and drain terminals. By increasing the number of fingers and channels created between them, and by increasing the peripheral area of the channels, with each channel having a maximized current capacity I
dss
, the power capacity of the entire FET can be increased. The power capacity is important in an SPDT switch application for the series connected FETs.
One of the most challenging specifications that a radio frequency (RF) switch used in commercial wireless applications must meet is linearity. Typically, the linearity of a series FET used in a switch is determined by its on state and off state harmonic suppression. However, linearity specifications can refer to the gain compression, third-order intercept point, the harmonic suppression of the switch, or a combination of these measures. Of these, harmonic suppression performance is the more difficult linearity specification to attain. Indeed, harmonic suppression is by far the most difficult, although important, aspect of linearity to meet in modern handset applications. In particular, high power Global System for Mobile Communications (GSM)/Digital Communication System (DCS) antenna switch specifications refer only to harmonic suppression in their linearity requirements.
On State Harmonic Performance
In order to improve the linear performance of a series FET when it passes a signal through it (i.e., when it is turned on), the I
dss
of the channel is increased. The “on state” series device in a switch must have a sufficient gate periphery to pass the short circuit RF current without distortion. This linearity factor is directly related to the I
dss
. Several methods are used in radio frequency applications to increase I
dss
. Gallium arsenide is commonly used as the base semiconductor material in radio frequency applications because it has the physical property of containing free carriers with higher mobility, which leads to an increased I
dss
. In the physical arrangement of a typical gallium arsenide FET, the gate consists of a conductive layer placed above the channel, between the ohmic connection points for the source and drain. By using a metal gate, better known as a Schottky barrier (as in a MESFET) rather than a junction (as in a JFET), the channel length can be further reduced. These approaches are combined to cooperatively increase the I
dss
of each channel.
To increase the gate periphery, typically the gate is laid down between the interdigitated source and drain fingers and around the ends of each finger, separating the source and the drain and covering the channel. Since the gate metalization spans the length of the channel, a decreased channel length produces a relatively narrow gate path. The narrow gate length increases the gate's impedance per unit of gate line. The gate appears as a long, serpentine line. This layout reduces the total area used by the device in an integrated circuit. By increasing the periphery of the series FET, the desired harmonic suppression for a given RF power level can be achieved at the expense of area used.
Off State Harmonic Performance
One problem associated with the series FET and the shunt FET occurs when the blocked RF signal voltage is of sufficient amplitude to overcome the desired effect of the control voltage applied to the gate (i.e., to inhibit the passage of the RF signal). An intrinsic capacitance between the gate and the drain, denoted C
gd
, and also between the gate and the source, denoted C
gs
, provides an electrical path for the signal to override the control voltage. These intrinsic capacitances act as conductors to superimpose the signal voltage over the control voltage at the gate. The linearity of the FET is determined by the difference between the pinch-off voltage (V
po
) and the control voltage applied to the switch. If the superimposed signal voltage is of sufficient magnitude to decrease the control gate voltage below V
po
, the gate will no longer be able to hold the FET off, and the signal will pass through the FET. Thus, a signal of sufficient magnitude can reverse a FET gated off and at least partially turn it back on. When a FET is undesirably turned on in this manner, harmonic signals are generated due to nonlinear characteristics of the device when operated with a control voltage near V
po
. These harmonic signals have frequencies two or more times the base frequency of the signal. Thus, the ability of the FET to suppress generation of harmonic signals may be impaired by the presence of this intrinsic capacitance.
In the prior art, the use of multiple gates addressed this problem by dividing the superimposed signal magnitude at each gate. Thus, if two gates were provided, the signal across each gate would be cut in half. Therefore, a signal of twice the magnitude as a signal that would overcome a single gate device would be required to overcome the control voltage and turn the dual gate FET back on. Because both gate lines must fit within the length of the channel, the lines will be narrower as well. Spacing between the lines narrowed the gate lines even further and the impedance per unit gate line increased. Because the control voltages used in modern cellular phones are typically on the order of three volts, this control voltage is insufficient to keep the FET pinched off under the stress of the RF signal, resulting in the production of unwanted harmonics, even with the benefit of multiple gates.
Another prior art solution that improved the linear performance of a multiple gate FET employed two feed forward capacitors connected between the drain and the gate nearest to the drain or between the source and the most proximal gate to the source respectively. The capacitors perfo
Arnold Brian Scott
Cooper Steven William
Abraham Fetsum
Anadigics Inc.
Pennie & Edmonds LLP
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