Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-12-26
2003-06-24
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S638000, C438S634000, C438S639000
Reexamination Certificate
active
06583047
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the prevention of photoresist poisoning during the formation of microelectronic devices.
2. Description of the Related Art
In the fabrication of microelectronic devices, it is known in the art to deposit various metal layers and insulation layers onto a substrate in selective sequence to form an integrated circuit (IC). As used herein, the term “microelectronic device” includes integrated circuits, intermetal dielectrics, and the like. Typically, a first level metal layer is deposited on a substrate, and is separated from a second level metal layer by one or more insulation layers. Subsequent metal layers may, in turn, be separated by one or more further insulation layers.
Insulation layers, which typically include dielectric materials such as silicon dioxide, silicon oxynitride, fluorinated silicate glass (FSG), spin-on glass (SOG) and the like, serve as electrical insulation between intermetal dielectric layers. These insulation layers are typically deposited by conventional techniques such as chemical vapor deposition (CVD) and the like, and serve as protective layers or gap fillers to achieve planarization of the substrate. The metal layers typically comprise conductive metals such as aluminum, copper, titanium, tantalum, tungsten and the like.
During the formation of these microelectronic devices, it is necessary to remove portions of the dielectric using standard photolithography and etching techniques. Trenches, vias, and the like are formed within the dielectric and are filled with conductive metals to form electrical connections with metal contacts in the integrated circuit. Upon such processing, the dielectric can come in contact with other materials, including but not limited to photoresist and antireflective coatings (ARC's).
One problem that arises from this contact between materials is that a reaction between the photoresist and certain dielectrics may occur. This is particularly important for a class of dielectric materials referred to as organosilicate glasses (OSGs), which includes trade name materials such as HOSP™, Black Diamond™ and Coral™. These materials can be either porous or non-porous These materials are extremely attractive in the industry as their dielectric constant is much lower than that of silicon dioxide. The reaction that occurs between the OSG and the photoresist/ARC creates a reaction product in vias which is difficult to remove by etching, ashing, and/or chemical stripping. As a result, the subsequent patterning of the interconnect structure is no longer defined by the photoresist and photoresist rework may become difficult or impossible. This phenomenon is known as “photoresist poisoning”, “resist poisoning”, “nailheading”, and/or “mushrooming”. Upon development, photoresist poisoning causes the exposed pattern areas of the photoresist layer to have a photoresist profile or structure with non-uniform side walls. Where a positive photoresist is used, photoresist poisoning often leads to the formation of a photoresist footing, or a widening of the photoresist line just above the substrate. Where a negative photoresist is used, photoresist pinching may result, which is a formation of non-uniform side walls of the photoresist profile on the underlying substrate after photolithographic exposure and development. After etching, such photoresist footing or photoresist pinching problem will lead to an imperfect transfer of the photoresist pattern to the underlying layer or layers. For some preferred methods of interconnect fabrication, in particular the dual Damascene process, this OSG/photoresist reaction can make interconnection formation difficult or impossible.
It would be desirable to devise a method of forming integrated circuits which avoids poisoning of the photoresist layer during resist formation. The subject of this invention is that the deposition or creation of an intermediate layer between the dielectric material and the photoresist inhibits the reaction which causes photoresist poisoning.
According to the present invention, the dielectric materials of the insulating layers are protected from the photoresist material to prevent chemical reactions which lead to photoresist poisoning. This is done by forming a modified surface layer on the dielectric material by either depositing an additional layer that covers the dielectric material, or by modifying the exposed surface of the dielectric material to a plasma or chemical treatment.
SUMMARY OF THE INVENTION
The present invention provides a process for producing a microelectronic device which comprises:
(a) forming a first dielectric layer on a substrate;
(b) forming an optional etch stop layer on the first dielectric layer;
(c) forming a second dielectric layer on the first dielectric layer or the optional etch stop layer;
(d) depositing a layer of a photoresist on a top surface of the second dielectric layer and imagewise removing a portion of the photoresist corresponding to at least one via for the first dielectric layer;
(e) removing the portions of each layer which are under the removed portions of the photoresist thus forming at least one via down through the first dielectric layer, and removing the balance of the photoresist layer;
(f) depositing a protective material on the top surface of the second dielectric layer and on inside walls and a floor of the via;
(g) depositing an additional layer of a photoresist on the protective material and imagewise removing a portion of the photoresist corresponding to at least one trench for the second dielectric layer;
(h) removing the portions of each layer which are under the removed portion of the additional photoresist layer thus forming at least one trench down through the second dielectric layer;
(i) removing the balance of the additional photoresist layer and the balance of the protective material;
(j) lining a barrier metal on inside walls and a floor of the trench, and on inside walls and a floor of the via; and
(k) filling the trench and via with a fill metal in contact with the barrier metal lining.
The present invention also provides a process for producing a microelectronic device which comprises:
(a) forming a first dielectric layer on a substrate;
(b) forming an optional etch stop layer on the first dielectric layer;
(c) forming a second dielectric layer on the first dielectric layer or the optional etch stop layer;
(d) depositing a layer of a photoresist on a top surface of the second dielectric layer and imagewise removing a portion of the photoresist corresponding to at least one via for the second dielectric layer;
(e) removing the portions of the second dielectric layer and the optional etch stop layer which are under the removed portions of the photoresist thus forming at least one via down through the second dielectric layer and the optional etch stop layer, and removing the balance of the photoresist layer;
(f) depositing a protective material on a top surface of the second dielectric layer and on inside walls and a floor of the via;
(g) depositing an additional layer of a photoresist on the protective material and imagewise removing a portion of the photoresist corresponding to at least one trench for the second dielectric layer;
(h) removing the portions of the protective material and the second dielectric layer which are under the removed portion of the additional photoresist layer thus forming at least one trench down through the second dielectric layer, and removing the portions of the first dielectric layer which are under the via which was in the second dielectric layer thus forming a via down through the first dielectric layer;
(i) removing the balance of the additional photoresist layer and the balance of the protective material;
(j) lining a barrier metal on inside walls and a floor of the trench, and on inside walls and a floor of the via; and
(k) filling the trench and via with a fill
Daniels Brian J.
Dunne Jude A.
Kennedy Joseph T.
Honeywell International , Inc.
Nguyen Ha Tran
Roberts & Mercanti LLP
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