Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2003-01-10
2003-11-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S048000, C438S051000, C438S060000, C438S075000, C257S231000, C257S232000, C257S233000
Reexamination Certificate
active
06642087
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-088971, filed Mar. 28, 2000; and No. 2000-302660, filed Oct. 2, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a solid state imaging device having a photodiode and a MOSFET and a method of manufacturing the same.
Many people have recently had an opportunity to capture, process and edit an image with ease as personal computers and personal digital assistants have sprung into wide use. For solid state imaging devices which are constituted chiefly of a CCD, the needs to decrease in size, power consumption and manufacturing costs have grown. To meet these needs, a MOS solid state imaging sensor, which is manufactured based on the general-purpose CMOS semiconductor technique (commonly called a CMOS image sensor), has made an appearance and started to become popular. The CMOS image sensor is currently fabricated with design rules of 0.35 &mgr;m or more. In the future, however, it is expected that the CMOS image sensor will be downsized further according to the needs to decrease in size and power consumption.
FIG. 29
is a cross-sectional view showing a prior art MOS solid state imaging device as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-150182. In
FIG. 29
, range A is a pixel region and range B is a peripheral circuit region.
As
FIG. 29
shows, polysilicon-made gate electrodes
13
a,
13
b
and
13
c
are selectively formed on a P-type silicon substrate
11
with a gate insulating film (silicon oxide film)
12
interposed therebetween. In the range A,
13
a
indicates a readout gate electrode and
13
b
denotes a reset or address gate electrode. Since a LOCOS (local oxidation of silicon) structure (hereinafter referred to as LOCOS) is generally used in a non-fine pattern formed with design rules of 0.35 &mgr;m or more, an element isolation region of the LOCOS structure is selectively formed in the silicon substrate
11
.
In the range A, an N-type drain region
14
a
and an N-type signal storage region
15
for a photodiode are formed in a desired area of the surface of the silicon substrate
11
. A P
+
-type surface shield region
21
is formed on the surface of the region
15
. Thus, P
+
NP-type buried photodiodes
34
a
and
34
b
for storing signal charges corresponding to an amount of incident light are formed. In the range B, an N-well and a P-well are formed in the silicon substrate
11
, and a P-type source and drain region
14
b
and an N-type source and drain region
14
c
are formed in the N-well and the P-well, respectively.
A first interlayer insulating film
25
is formed on the entire surface of the resultant structure, and a second interlayer insulating film
27
is formed on the film
25
. An Al light-shielding film
28
is formed on the film
27
. The film
28
has an opening
30
through which light is incident upon the photodiodes
34
a
and
34
b.
An Al wiring layer
26
is selectively formed in the second interlayer insulating film
27
and on the first interlayer insulating film
25
. The layer
26
serves as a signal line and a connection line in units of pixels. A surface protection film
29
such as a silicon nitride film is formed on the top of the structure. In some cases, intermediate refracting films such as Ti and TiN films can be provided on the tops and undersides of the Al wiring layer
26
and the Al light-shielding film
28
to prevent light from being reflected therefrom (as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-45989).
In the MOS solid state imaging device so constituted, the signal charges stored in the signal storage region
15
are read out of the N-type drain region
14
a
if a positive voltage is applied to the readout gate electrode
13
a,
thus modulating the potential of the drain region
14
a.
The region
14
a
is electrically connected to the gate electrode
13
b
of an amplification transistor, and an electrical signal amplified by the gate electrode
13
b
is output from the Al wiring layer
26
of the signal line.
However, stray light produces a greatly adverse effect as one problem caused when the pixels are downsized further in the prior art solid state imaging device described above.
The stray light means part of light incident upon the photodiodes
34
a
and
34
b
which is reflected by the surface of the silicon substrate
11
and then multi-reflected by the surfaces of the Al wiring layer
26
, drain region
14
a
and gate electrode
13
b
and which goes in the distance. In the device shown in
FIG. 29
, the surfaces of the gate electrodes
13
a
to
13
c
and those of the source and drain regions
14
a
to
14
c
are made of silicon materials whose reflectivity is as high as 40% or more in a visible-light region. For this reason, stray light reflected by the surface of the photodiode
34
a
does not attenuate sufficiently but reaches its adjacent photodiode
34
b,
thereby causing a false signal such as smear and blooming.
If an interval between the photodiodes
34
a
and
34
b
shorten as the pixels decrease in size, it is natural that more intensive stray light enters a nearer photodiode, with the result that a false signal such as smear and blooming is easy to occur. Since the stray light does not attenuate sufficiently, it arrives at the source and drain regions
14
b
and
14
c
and the gate electrode
13
c
in the peripheral circuit region (range B) to cause the transistor to malfunction. In future, therefore, an adverse effect of the stray light will be increased more greatly as the pixels are downsized.
Currently the CMOS image sensor employs a power supply voltage of 3.3V or higher. It is expected that a CMOS image sensor operating at a power supply voltage of 3.3V or lower will be developed according to the above micromachining of 0.35 &mgr;m or less in order to decrease the size and power consumption of the solid state imaging device further.
However, using a buried photodiode structure in which a surface shield region of a conductivity type other than that of the signal storage region is formed on the surface of the photodiode, the problem of a decrease in power supply voltage of the readout gate electrode will become more serious.
FIG. 30A
is a cross-sectional view of the buried photodiode which is part of the range A in FIG.
29
.
FIGS. 30B and 30C
show potentials in low-voltage read mode (when the read gate electrode turns on). In
FIG. 30C
, charges are read out at a voltage lower than that in FIG.
30
B.
As
FIG. 30A
illustrates, an element isolation region of the LOCOS structure is selectively formed in the P-type silicon substrate
11
, and the readout gate electrode
13
a
is selectively formed on the silicon substrate
11
with the gate insulating film
12
, such as a silicon oxide film, interposed therebetween. The N-type drain region
14
a,
N-type signal storage region
15
and P
+
-type surface shield region
21
are formed on the surface of the silicon substrate
11
by ion implantation. Thus, the photodiode
34
a
is obtained. Both the silicon substrate
11
and the surface shield region
21
are grounded at a reference potential.
In the solid state imaging device described above, when light is incident upon the photodiode
34
a,
the incident light is photoelectrically converted into a signal electron, and the signal electron is stored in the signal storage region
15
. The surface shield region
21
serves to both prevent an interface of the gate insulating film
12
between Si and SiO
2
from being depleted to reduce junction leakage currents and to set potential
42
of the signal storage region
15
between the surface shield region
21
and silicon substrate
11
lower than channel potential
43
under the gate electrode
13
a
which is modulated by turning on the readout gate electrode
13
a.
In principle, the signal electrons can completely be transferred from the signal storage region
15
to the
Inoue Ikuko
Nozaki Hidetoshi
Yamashita Hirofumi
Kabushiki Kaisha Toshiba
Nelms David
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Mai-Huong
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