Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-01-25
2003-06-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S640000, C438S701000, C438S713000
Reexamination Certificate
active
06583055
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a contact forming method for a semiconductor device. More particularly, it relates to a method of forming a stepped contact trench with doped trench sidewalls.
2. Description of the Related Arts
One important technique for fabricating a semiconductor device involves forming a connection between an upper level wiring layer and either a conductive region of an impurity-diffused layer in a semiconductor substrate or a lower level wiring layer. Such a connection is preferably formed through a contact hole formed in interlayer insulating film.
As the density of integrated circuits has increased, the design rule, i.e., the minimum feature size, has decreased. With this increasing scale of integration of semiconductor devices, the diameters of contact holes are accordingly being made even smaller; however, it is difficult to reduce the depths of contact holes because of the need for wiring resistance or capacity. For this reason, the aspect ratios of contact holes have rapidly increased in recent years, and there has been a high demand for forming metal electrodes featuring good coverage.
FIGS. 1A
to
1
C are cross-sections at selected stages of a conventional fabrication process for forming a contact trench and a barrier metal film. Referring to
FIG. 1A
, on a semiconductor substrate
10
, an interlayer dielectric (ILD) layer
14
is provided with a cap layer
12
interposed. The ILD layer
14
generally consists of one or more dielectric depositions of spin on glass (SOG), silicon oxide; borophosphosilicate (BPSG), and so on. The cap layer
12
, serving as a diffusion barrier to prevent diffusion of impurities in the ILD layer
14
into the substrate
10
, is typically silicon nitride (SiN), though other materials may be used.
Next, as illustrated in
FIG. 1B
, a contact opening
16
is etched through the ILD layer
14
and the cap layer
12
using a photoresist pattern as a mask. The etching is further carried into the substrate
10
to a predetermined depth to form a trench portion
16
a
below the substrate surface. Here, because the silicon nitride cap layer
12
is less liable to be etched as compared with the substrate
10
and the ILD layer
14
, an overhang configuration H is created within the contact hole
16
.
Thereafter, a conventional method of forming a contact is by sputtering a Ti/TiN barrier layer
18
over the ILD layer
14
and over bottom and sidewalls of the contact hole
16
. However, as illustrated in
FIG. 1C
, the overhang H makes sputtering of the barrier layer very difficult. The step coverage of the Ti/TiN layer
18
is especially poor on sidewalls of the trench
16
a
. The insufficient coverage of Ti/TiN barrier
18
leads to high contact resistance and yield problems, and stable electrical characteristics of a contact electrode cannot be obtained. In addition, as the trench widths have gotten progressively smaller recently, the devices have become subject to additional leakage paths caused by formation of parasitic edge transistors at upper edges of the trench sidewalls. Parasitic edge transistors are not desired because they increase the OFF current of the devices and increase the susceptibility to latchup.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of forming a contact trench which provides better step coverage.
Another object of the invention is to provide a method of forming a contact trench which overcomes the parasitic transistor problem.
The above and other objects of the invention are accomplished by forming a contact trench with stepped sidewalls and by implanting dopants into trench regions before the trenches are etched.
In one preferred embodiment of the invention, the stepped contact trench is formed by: forming a cap layer on a semiconductor substrate; sequentially forming a first dielectric layer and a second dielectric layer on the cap layer; etching a preliminary contact hole through the second dielectric layer and the first dielectric layer; implanting dopants in the substrate through the preliminary contact hole and then annealing to diffuse the dopants to form a doped region; etching to remove the cap layer exposed by the preliminary contact hole; etching the substrate underneath the preliminary contact hole to form a trench with the doped region provided at the upper edges of the trench; isotropically etching the sidewalls of the preliminary contact hole with an etching agent having a higher etch rate for the second dielectric layer than for the first dielectric layer, thereby forming a contact hole with a stepped sidewall; and etching to remove the cap layer exposed by the stepped contact hole.
In another preferred embodiment of the invention, the stepped contact trench is formed by: forming a cap layer on a semiconductor substrate; sequentially forming a first dielectric layer and a second dielectric layer on the cap layer; etching a preliminary contact hole through the second dielectric layer and the first dielectric layer; etching to remove the cap layer exposed by the preliminary contact hole; implanting first dopants in the substrate through the preliminary contact hole and annealing to diffuse the dopants to form a first doped region; isotropically etching the sidewalls of the preliminary contact hole with an etching agent having a higher etch rate for the second dielectric layer than for the first dielectric layer, thereby forming a contact hole with a stepped sidewall; optionally implanting second dopants in the substrate through the stepped contact hole and then annealing to diffuse the dopants to form a second doped region; etching the substrate underneath the stepped contact hole to form a trench with the first doped region provided at the upper edges of the trench; and etching to remove the cap layer exposed by the stepped contact hole.
REFERENCES:
patent: 5180689 (1993-01-01), Liu et al.
patent: 5203957 (1993-04-01), Yoo et al.
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5604159 (1997-02-01), Cooper et al.
patent: 5872053 (1999-02-01), Smith
patent: 5888887 (1999-03-01), Li et al.
patent: 6444574 (2002-09-01), Chu
Gurley Lynne A.
Ladas & Parry
Niebling John F.
Powerchip Semiconductor Corp.
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