SRAM with improved noise sensitivity

Details SRAM with improved noise sensitivity SRAM with improved noise sensitivity

2002-05-14

2003-11-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S206000, C365S188000, C365S230030, C365S230060

Reexamination Certificate

active

06654277

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to static random access memories (SRAMs) and more particularly to improving noise sensitivity in SRAM cells.
2. Background Description
Invertors made completely of n-type enhancement mode field effect transistors (NFETs) or devices, such as inverter
20
of
FIG. 1
are well known in the art. A typical NFET invertor
20
is two series connected NFETs
22
,
24
. The first NFET
22
is tied gate to drain between a supply voltage (V
dd
) and an output
26
. The second NFET
24
is connected drain to source between a low supply or reference voltage (ground, GND) and the output
26
. The input
28
to the invertor
20
is provided to the gate of the second NFET
24
.
With the input low, both FETs
22
,
24
are off and the output is high, below V
dd
by the NFET threshold voltage (V
T
), i.e., at V
dd
−V
T
. When the input to the invertor
20
is driven high, the second NFET
24
turns on and, at steady state is in its linear or resistive operating range (R
on
), pulling the output
26
low. The first NFET is also on, but in saturation, acting as a voltage controlled current source (I
sat
) The output down level (V
low
) under these conditions is the voltage drop across the resistive second transistor
24
by the current supplied by the voltage controlled current source of the first transistor
22
, i.e., V
low
=I
sat
R
on
. Calculating these parameters is well known in the art and is dependent upon device operating conditions and numerous technology dependent device characteristics.
Some of these device characteristics, e.g., gate oxide thickness, are common to both transistors
22
,
24
. However, the individual transistors
22
,
24
each have individual device characteristics and bias conditions that affect V
low
, e.g., each device's width to length ratio (W/L), gate, source and drain operating voltages and substrate bias voltage. A typically acceptable output down level is a voltage level that is somewhat less than V
T
such that the circuit driven by the invertor output
26
experiences a low, i.e., the next driven NFET does not turn on.
For simplicity in design, since at steady state the output is constant at V
low
very often each of the NFETs
20
,
24
are modeled as resistors (transconductances) in a voltage divider. Accordingly, the output down level may be treated as the voltage from this voltage divider. Further, the ratio of these two transconductances may be referred to as the beta (&bgr;) ratio of the invertor. The &bgr; ratio can be used to provide a measure of acceptability of the two devices
22
,
24
as an invertor, i.e., a “rule of thumb.” For example, an invertor with a &bgr; ratio of 1 has an output down level that is V
dd
/2. An invertor with a &bgr; ratio of four has an output down level of 0.2V
dd
.
FIG. 2
shows an example of a typical state of the art six transistor (6T) static random access memory (SRAM) cell
50
, in the well-known complementary insulated gate FET technology known as CMOS. Data is stored in a pair of cross-coupled invertors
52
,
54
. NFET
52
N and p-type FET (PFET)
52
P form the first invertor
52
. NFET
54
N and PFET
54
P form the second invertor
54
. A pair of pass gates
56
,
58
are connected between each of the cross coupled invertors
52
,
54
and a respective bit line pair
60
,
62
. A word line
64
, connected to numerous SRAM cells
50
, controls the gates of pass gates
56
,
58
. Typically, the bit line pair
60
,
62
are connected to numerous identical SRAM cells
50
, each connected to a different word line. The capacitive load for the bit line cells is modeled by a pair of capacitors
66
,
68
. Each cell
50
is addressed/selected by intersection of the word line
64
at a bit line pair
60
,
62
.
In a typical SRAM array, a single word line
64
drives pass gates
56
,
58
for numerous cells
50
, each connected to individual pairs of bit lines
60
,
62
. Typically, anytime the word line is driven, only a subset of all of the cells at specific selected columns on the word line are of interest. Other cells on the word line at columns other than selected columns are also connected to their bit lines, typically referred to as half selected cells. The half selected cells are connected to their pre-charged bit line pairs with the bit line pairs precharged and floating at V
dd
. Half selected cells should retain data after selection, identically to what is stored in them prior to half selection. A cell disturb, e.g., from incomplete precharge or a design imbalance, cells may switch states.
Data is written into the cell
50
by driving one of the bit line of the pair,
60
,
62
high, pulling the other low and, subsequently, driving the word line
64
high for a short period of time. With the word line
64
high, the state of the bit line pair
60
,
62
is transferred to cross coupled invertors
52
,
54
. With the word line
64
low, that state is stored in the cell
50
.
Reading data stored in the cell is, more or less, the reverse of a write. First, the bit lines are pre-charged to some bit line pre-charge voltage level (V
pre
), typically V
dd
. After the bit lines are pre-charged, pre-charging the bit line capacitance is
66
,
68
, the bit lines are floated at the pre-charged and then the word line
64
is driven high. Whatever is stored in the cell, as represented by the respective complementary states of a cross coupled invertors
52
,
54
, is transferred to the bit lines
60
,
62
as a voltage difference. Depending on the state of the cross couple invertors
52
,
54
, a corresponding bit line
60
or
62
, eventually is pulled low and the remaining bit line
62
or
60
remains high. How fast the bit line is pulled low determines cell read time or read performance.
During a read, when the word line
64
turns on, both pass gates
56
,
58
connect the cell storage nodes at the cross couple invertors
52
,
54
to the bit line pair
60
,
62
. At least at the beginning of the read with both bit lines of the pair
60
,
62
and the word line high, one of the cross coupled invertors
52
,
54
(i.e., the invertor driving a low) is biased identically to the NFET inverter
20
of FIG.
1
. Thus, cell stability depends on the &bgr; ratio of the particular pass gate/inverter NFETs
56
/
52
N and
58
/
54
N. Cell performance also depends on the &bgr; ratio for the pair of NFETs
56
,
52
N or
58
,
54
N pulling down the particular bit line
60
or
62
respectively.
Primary concerns of SRAM cell design are cell size, cell performance and cell stability. Cell size is usually a function of the particular geometry or minimum feature size available for the technology in which the cell is being made. Performance and stability are also affected by cell size. To minimize read time and, therefore, optimize performance, the resistance of both pass gates and inverter NFETs (
52
N,
54
N,
56
,
58
) should be minimized. Typically, invertor NFETs
52
N,
54
N are a minimum sized devices. So, most read performance is realized by reducing the resistance of pass gates
56
,
58
. However, reducing the pass gate resistance increases transconductance, reducing &bgr; ratio and stability, e.g., by increasing the half select voltage drop across the internal cell NFETs
52
N,
54
N. Further, at some point &bgr; ratio may be low enough that even minor noise may cause the half selected cell to switch, inadvertently changing data stored in the cell. Generally, the cell beta ratio is selected between two and four, making SRAM cells are more stable and tolerant to noise and other disturbances, e.g., during a cell read. Also, in this &bgr; ratio range, the cell remains relatively insensitive to other sources of errors, e.g., alpha-particles or soft errors. Unfortunately, a more stable cell is harder to switch, thus increasing cell write time and also, this stability is at a cost of cell read performance which is not a particularly desirable tradeoff.
Cells with a beta ratio below 1.5 are considered sensitive with disturb occu

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