Reducing leakage currents in integrated circuits

Details Reducing leakage currents in integrated circuits Reducing leakage currents in integrated circuits

2001-04-30

2003-02-04

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S095000

Reexamination Certificate

active

06515513

ABSTRACT:

TECHNICAL FIELD
This invention relates to reducing leakage currents in integrated circuits.
BACKGROUND
Standby leakage current is the current which may flow through a logic circuit when a transistor within the circuit is at high impedance and attempting to hold an output voltage at a certain level. Standby leakage current can cause a loss of the signal output and can also increase power consumption of the logic circuit.
Referring to
FIG. 1
, an approach to reducing standby leakage current in CMOS circuits was proposed in Mutoh, et al., “1-
V Power Supply High-Speed Digital Circuit Technology with Multithreshold
-
Voltage CMOS
”, IEEE Journal of Solid-State Circuits, Vol. 30, No.8, August 1995, pp. 847-854. Mutoh, et al, proposed a CMOS logic circuit
100
including a series of CMOS logic gates
102
A-
102
B. Logic circuit
100
includes ‘sleep’ transistors Q
1
and Q
2
, which are connected between the supply voltage, Vdd, and common ground, GND, respectively, to establish ‘virtual’ supply lines, VDDV and GNDV. The source terminals
104
A-
104
B of the p-block transistors of each CMOS logic gate
102
A-
102
B are connected to VDDV, while the source terminals
106
A-
106
B of the n-block transistors are connected to GNDV. By P-block (or N-block) is meant a circuit that includes one or more p-channel (or n-channel) transistors.
In operation, in ‘sleep mode’, SL
120
is at logic-level ‘1’, which turns off the sleep transistors Q
1
and Q
2
and cuts off the leakage current that would otherwise pass through the logic gates
102
A-
102
B. In ‘active mode’, SL
120
is at logic-level ‘0’, turning on Q
1
and Q
2
, allowing the logic gates
102
A-
102
B to evaluate. When in ‘active’ mode, the sleep transistors produce a VDDV which is lower than Vdd due to a voltage drop through Q
1
, and produce a GNDV which is higher than common ground due to a voltage drop through Q
2
. As a result, the effective voltage seen by the logic circuits
102
A-
102
B is less than the difference between Vdd and common ground. This lower effective voltage increases the evaluation time of CMOS logic gates
102
A-
102
b and therefore reduces the overall speed of the logic circuit
100
.


REFERENCES:
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 5999019 (1999-12-01), Zheng et al.
patent: 6154045 (2000-11-01), Ye et al.
patent: 2002/0008999 (2002-01-01), Hidaka
Shin ichiro Mutoh et al. 1-V Power supply High-Speed Digital Circuit Technology with Multithrehold-Voltage CMOS, IEEE Journal of Solid-State Circuits, vol. 30, No. 8, Aug., 1995.
Hiroki Morimura et al. A Step-Down Boosted-Wordline Scheme for 1-V Battery-Operated Fast SRAM's, IEE Journal of Solida-State Circuits, vol. 33, No. 8, Aug. 1998.
Y. Oowaki et al. “TP 6.2: A Sub-0.1 &mgr;m Circuit Design with Substrate-over-Biasing”, 1998 IEEE International Solid-State Circuits Conference, First Edition, IEEE Catalog No., 98CH36156, Feb., 1998.

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