Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2002-08-05
2003-11-04
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S001000, C710S020000, C710S029000, C710S036000, C710S058000, C711S167000, C712S040000, C712S225000, C713S400000, C713S600000
Reexamination Certificate
active
06643720
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of controlling the transfer of a variety of information such as instruction information or data information between a memory or a peripheral circuit and a data processor, and a peripheral circuit, a data processor and a data processing system using the method, and, more particularly, to a technique which is especially effective if applied to the control technique of the data transfer between the data processor and a memory. Incidentally, the data processor in the present Specification will cover the general concept of a CPU (i.e., Central Processing Unit), a microprocessor, a microcomputer, a single-chip microcomputer, a digital-signal processor or a direct memory access controller.
SUMMARY OF THE INVENTION
Some RISC processors of the prior art include one or more cache memories in a chip from the point of view of performance, cost, manufacture process and technical level of the LSI. Such a CPU is connected with a number of memories and input/output) circuits on a circit board to construct a system. It is usual to use an operation clock (or system clock) as a reference to the operation of the system. Usually, the peripheral circuits such as the memories and the input/output circuits to constitute the system are individually given different functions and characteristics to have individually different operating procedures, response times or operating speeds. It is needless to say that the CPU interfaces owned by the memories and the input/output circuits are frequently different from one another although they have some similarity in the functions or timings.
As to the differences in such functions, operating speeds and interface specifications, memory controllers are used for the memories, and I/O controllers are used for the input/output circuits. These controllers have functions, as roughly divided into the following two points.
The first function is to inform the memories and the input/output circuits of which memory or input/output circuit is selected by the CPU, and initiates a data transfer. This function can be regarded as the so-called “chip selection” or “chip enable control”. For example, logic operations between the signals indicating the kinds of addressing and access are carried out to produce pulses or level signals by using an operation clock or the like thereby to activate only the memory selected or the signal connected with the input/output circuit.
The second function is to count the operation clocks by a counter thereby to produce a signal demanding the CPU for an extension of the access period at the unit of the operation clock for the wait or ready operation. Under to the rule of confirming the signal for each operation clock by the CPU, the difference in the timing or the operation speed between the CPU and the memory or the peripheral circuit is absorbed to realize the data transfer without fail. This function is the so-called “wait state control function”.
However, we have revealed that the aforementioned wait state function by the controller has the following problems.
(1) Since the duration of the data transfer time to be extended by the wait state is always determined at the operation clock unit of the system, it is impossible to sufficiently extract the performance intrinsic to the memory or peripheral circuit. Moreover, it is substantially impossible to design the system by using the performance, which is based upon the design data submitted by the maker/seller as to the memory or the input/output circuit, in the limit state. Since a certain operation margin is considered, a data transfer involves idle time in most cases so that the data transfer efficiency on the data bus decreases. This problem applies not only to the case in which-the system is constructed on a circuit board, i.e., in which the connections between the memories or the input/output circuits and the CPU are made through the buses on the board, but also to the case in which the CPU and the memories are formed over a common semiconductor chip. Specifically, if an optimum design were to made considering the electric characteristics and the arrangement of circuit elements, the controllers and the memories could effect the data transfer efficiently to the operation clock of the controllers. In the actual circuit design, however, a delicate timing has to be made in the chip although not easy, while considering the characteristics of the individual logic circuit blocks.
(2) The aforementioned wait state control takes serious troubles because the designer has to design the system for the individual memories or input/output circuits, if in plurality, due to the differences in the functions (including the protocol) and performances.
(3) The circuit portions required for the wait state control have to cover the sets of memories and input/output circuits, thus causing difficulties in the high speed, the small size and the low prices such as the complicatedness of the system, the increase in the part number or the increase in the load upon the signal line.
(4) As has been described in the aforementioned problem (1), the wait state control cannot sufficiently extract the performances intrinsic to the memories and the peripheral circuits so that it limits the speed-up of the operations. In order to eliminate this limit, therefore, all or the highly efficient memories or input/output circuits could be connected without the wait state control. If, however, the operation clock of the controller is suppressed according to the characteristics such as the operation speed of the memories and the input/output circuits, the controller such as the CPU has a tendency to have its operation clock speeded up to drop the value of the system. If, on the contrary, a fast memory or input/output circuit is to be used in conformity to the operation clock of the controller, an extremely high rise is caused in the system price.
Thus, the system of the prior art for producing the timing of the data transfer between the CPU and the peripheral circuit from the operation clock of the CPU or the system cannot realize the data transfer which can sufficiently exploit the intrinsic performance of the peripheral circuit such as the memory. Specifically, we have thought it difficult to desire a basic development to a high speed if the CPU and the peripheral circuit are connected by the wait state control function which stresses the reliable operation by returning the wait signal to the CPU at a timing of integer times as high as that of the operation clock on the basis of the characteristics of the peripheral circuit.
An object of the present invention is to provide a technique which is enabled to effect a data transfer by sufficiently exhibiting the intrinsic characteristics owned by a peripheral circuit such as a memory.
Another object of the present invention is to provide a peripheral circuit for producing a timing of the data transfer according to its own characteristics.
A further object of the present invention is to provide a data processor capable of transferring data efficiently with such peripheral circuit.
A further object of the present invention is to provide a data processing system capable of transferring data fast with the data processor by sufficiently exhibiting the intrinsic characteristics owned by the peripheral circuit such as the memory.
The aforementioned and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
A representative of the invention to be disclosed herein will be briefly described in the following.
Specifically, as represented in
FIG. 1
, a memory (
1
) acting as a peripheral circuit performs its internal operation in accordance with access requests (
200
,
201
and
202
) from a CPU (
2
) exemplifying the data processor, and in synchronism with the output signal of a self-excited oscillator (
102
) incorporated therein; and outputs a response requests (
103
) to the data processor in synchronism with that int
Gaffin Jeffrey
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Nguyen Tanh Q
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