Mode adaptive data output buffer for semiconductor memory device

Details Mode adaptive data output buffer for semiconductor memory device Mode adaptive data output buffer for semiconductor memory device

1996-06-27

1997-09-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

36518905, G11C 700

Patent

active

056639147

ABSTRACT:
A mode adaptive data output buffer for a semiconductor memory device, the semiconductor memory device having a plurality of memory cells for storing data therein, comprising true end complementary data lines for inputting true and complementary data read from the memory cells, respectively, a control line for inputting an output enable signal for controlling the output of the true and complementary data read from the memory cells, first and second pull-up drivers connected in parallel between a first voltage source and an output line, first and second pull-down drivers connected in parallel between a second voltage source and the output lane, a PMOS transistor for switching the second pull-up driver to the output line, an NMOS transistor for switching the second pull-down driver to the output line, and a controller for detecting the input order of the true and complementary data read from the memory cells and the output enable signal and controlling the PMOS and NMOS transistors in accordance with the detected result. The controller includes a data transition detector and a latch circuit. According to the present invention, the mode adaptive data output buffer is capable of performing a high-speed operation and minimizing the generation of noise regardless of a data mode.

REFERENCES:
patent: 5073872 (1991-12-01), Masuda
patent: 5311076 (1994-05-01), Park
patent: 5315173 (1994-05-01), Lee et al.
patent: 5325330 (1994-06-01), Morgan
patent: 5414312 (1995-05-01), Wong

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