Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-04-07
2003-10-14
Kim, Hong (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S154000, C711S005000, C711S105000, C713S401000, C713S501000, C713S502000, C713S503000, C365S233100, C365S193000, C365S194000
Reexamination Certificate
active
06633965
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to the field of memory controllers.
BACKGROUND OF THE INVENTION
The purpose of a memory controller is to field and execute memory access requests (i.e., requests to read data from, and write data to, a number of memory modules). A memory access request is typically initiated by a central processing unit (CPU), but one may also be initiated by an input/output device (I/O device).
In the past, most memory controllers have been designed to access memory modules which are read and written via common clock data transmissions. That is, data bits are transmitted between a memory controller and a number of memory modules in sync with the rising edges of the memory controller's internal clock. However, there is a current push to design memory controllers which are capable of accessing double data rate (DDR) memory modules.
A DDR memory module is one which is read and written via source synchronous data transmissions. That is, data bits are transmitted between a memory controller and a number of memory modules in sync with the rising and falling edges of a strobe, with the strobe being generated by the component which sources the data. The strobe is then used by the component which receives the data for the purpose of capturing the data. Thus, a strobe is transmitted by the memory controller during a write operation, and a strobe is transmitted by a memory module during a read operation.
SUMMARY OF THE INVENTION
As is known by those skilled in the art, the complexity of memory controllers makes them very expensive components to design, develop and verify. The inventors therefore provide below a description of a memory controller having a greater number of functional modes. By providing a memory controller with a greater number of functional modes, an application specific integrated circuit (ASIC) manufacturer can satisfy a greater number of computing applications with a single memory controller, and thus save time and expense by designing, building and testing a fewer number of memory controllers. From a computer manufacturing perspective, the use of a common memory controller in a variety of computer systems enables machine dependent code, printed circuit board design, et cetera to be leveraged from one computer system to the next.
In accordance with the invention, new methods and apparatus pertaining to memory controllers are disclosed herein. A portion of the methods and apparatus pertain to a memory controller's reading of data from a number of memory modules.
In general, the methods and apparatus provide a memory controller with means for receiving data at different rates (e.g., 1× and M× rates). Data may be received by a memory controller at different rates because, for example, the memory controller is used in environments where it attaches directly to a number of memory modules, and/or in environments where it attaches to a number of memory modules via an intermediary chip. The intermediary chip may, for example, comprise multiplexers which receive data from two or more banks of memory modules and then multiplex the data into one or more data streams which are then transmitted to the memory controller at twice the rate which the memory modules in either bank could transmit data to the memory controller.
Although the invention is not limited to DDR environments, one embodiment of the invention provides a double data rate memory controller which comprises means for receiving data and strobe signals at 1× double data rate memory speed, and means for receiving data and strobe signals at M× double data rate memory speed (where M≧2 and x is a conventional rate at which DDR data is received by receiver circuitry).
Another embodiment of the invention provides memory controller receiver circuitry with a data pad and a strobe pad (which pads may form part of an interface comprising a plurality of data and strobe pads). P storage elements (e.g., latches; P≧2) are coupled to receive data from the data pad. The P storage elements are controlled by respective values of a count which is preferably a P bit, one-high count. The count is updated by a counter in response to strobe edges of strobe signals received at a strobe pad. In this manner, the P storage elements operate in the clock domain of memory modules and/or intermediate chips which are attached to the receiver circuitry. A deskew multiplexing stage is provided for receiving data from the P storage elements. Unlike the P storage elements, however, the deskew multiplexing stage receives control signals which are generated in a clock domain of the receiver circuitry (i.e., a clock domain of the memory controller of which the receiver circuitry forms a part). If P is equal to four, and the multiplexing stage comprises two deskew multiplexers which receive data from the P storage elements, then a first of the deskew multiplexers may be provided with control signals which change at a 1× rate, thereby allowing data bits received at a 1× rate to propagate through the first deskew multiplexer. When 2× data is received by the receiver circuitry, then both of the deskew multiplexers may be provided with control signals which change at a 1× rate, thereby allowing data bits received at a 2× rate to alternately propagate through the first and second deskew multiplexers (i.e., consecutive data bits are clocked out of alternate ones of the deskew multiplexers).
A third embodiment of the invention provides a method for receiving data into a memory controller. The method commences with receiving data bits presented to a data pad of a memory controller into respective ones of P storage elements (again, where P≧2). The data bits are received in response to a count of strobe edges received at a strobe pad of the memory controller. As data stored in the P storage elements is output to a number of deskew multiplexers, control signals for the deskew multiplexers are generated in a clock domain of the memory controller.
One advantage of the memory controller and receiver circuitry disclosed herein is that it adapts to receiving 1× or M× (e.g., 2×) data using relatively simple hardware. By providing a memory controller that can read data in 1× and M× modes, a more universal memory controller may be manufactured, thus scaling to increase the range of market segments covered by the memory controller with only a minimal increase in manufacturing costs.
Another advantage of the disclosed circuitry is that it can scale to support higher bandwidth, higher capacity systems.
Yet another advantage of the disclosed circuitry is that increasing values of P provide increased times for deskewing data which is received at a data pad (i.e., increased times for transferring control of the data from a clock domain of a memory module or intermediate chip, to a clock domain of the memory controller). Thus, greater variations in read data timing are tolerated.
The important advantages and objectives of the above and other embodiments of the invention will be further explained in, or will become apparent from, the accompanying description, drawings and claims.
REFERENCES:
patent: 5522064 (1996-05-01), Aldereguia et al.
patent: 5727005 (1998-03-01), Le et al.
patent: 5809340 (1998-09-01), Bertone et al.
patent: 5974499 (1999-10-01), Norman et al.
patent: 6065132 (2000-05-01), Takano
patent: 6125078 (2000-09-01), Ooishi et al.
patent: 6288971 (2001-09-01), Kim
patent: 6338113 (2002-01-01), Kubo et al.
patent: 6370630 (2002-04-01), Mizuyabu et al.
patent: 6480946 (2002-11-01), Tomishima et al.
patent: 6530001 (2003-03-01), Lee
patent: 6532525 (2003-03-01), Aleksic et al.
patent: 2001/0046163 (2001-11-01), Yanagawa
patent: 2002/0147896 (2002-10-01), Rentschler et al.
patent: 2002/0147898 (2002-10-01), Rentschler et al.
patent: 2002/0172079 (2002-11-01), Hargis et al.
patent: WO 99/04494 (1999-01-01), None
“Preliminary Publication of JEDEC Semiconductor Memory Standards—DDR SDRAM Specification”, Aug. 1999 (73 page).
JEDEC Standard No. 7
Hargis Jeffrey G.
Johnson Leith L.
Rentschler Eric M.
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