Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-02-16
2003-11-18
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S154000
Reexamination Certificate
active
06651152
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer including a download circuit (referred to as “DLC” hereinafter) controlling data input and output with a memory apart from a central processing unit (referred to as “CPU” hereinafter). Particularly, the present invention relates to a microcomputer that allows data input/output with respect to a memory without complex control and mechanism.
2. Description of the Background Art
Referring to
FIG. 1
, a conventional microcomputer with a DLC circuit includes a CPU
1
, a register group
3
, a DRAM (Dynamic Random Access Memory)
4
, an SRAM (Static RAM)
5
, a flash memory (Flash-ROM (Read-Only Memory))
6
, a BIU (Bus Interface Unit)
2
provided between CPU
1
and each of memories
3
,
4
,
5
and
6
, a DLC
48
to write data (download) to flash memory
6
and read out data from flash memory
6
, a mode set circuit
8
responsive to an external signal
21
for mode setting to output an internal mode set signal A setting the operational mode of the microcomputer to a download mode, a reset signal generation circuit
9
to generate and apply to CPU
1
, BIU
2
, register group
3
, DRAM
4
and SRAM
5
a reset signal
15
in response to an external signal
22
for resetting, an AND gate
41
having a first input coupled to reset signal
15
and a second input coupled to an inverted version of internal mode set signal A to output a reset signal
16
, and a selector
11
having a first input receiving a bus group
12
and a second input receiving a flash memory control signal group
13
, under control of internal mode set signal A.
Selector
11
is under control of internal mode set signal A provided from mode set circuit
8
. Selector
11
connects control signal group
14
of the flash memory from selector
11
to flash memory control bus group
12
when internal mode set signal A is at an L level (logical low). Selector
11
connects control signal group
14
of the flash memory to flash memory control signal group
13
when internal mode set signal A is at an H level (logical high).
This conventional microcomputer has DLC
48
rewrite data in flash memory
6
during reset as set forth in the following.
First, an external signal
22
for reset is applied to reset signal generation circuit
9
. Reset signal generation circuit
9
provides reset signal
15
of an H level. In response to reset signal
15
attaining an H level, CPU
1
, BIU
2
, register group
3
, DRAM
4
and SRAM
5
are all reset and stop operation. This reset signal
15
of an H level is also applied to the first input of AND gate
41
. Assuming that internal mode set signal A output from mode set circuit
8
is at an L level (non-download mode), the other input of AND gate
41
is inverted to an H level. Therefore, reset signal
16
outputted from AND gate
41
attains an H level, whereby flash memory
6
is reset and stops operation.
Then, external signal
21
to set the microcomputer to a download mode is applied to mode set circuit
8
. Mode set circuit
8
outputs internal mode set signal A of an H level. This internal mode set signal A is inverted and applied to the second input of AND gate
41
. Therefore, the output of AND gate
41
attains an L level, whereby flash memory
6
attains an operable state. More specifically, AND gate
41
provides an output of an H level during reset and in a download mode, and otherwise an L level.
Since internal mode set signal A is at an H level, selector
11
connects flash memory control signal group
13
to control signal group
14
of the flash memory, so that DLC
48
can control flash memory
6
. Under this state, data in flash memory
6
is rewritten via DLC
48
according to an external signal
20
for the DLC. DLC
48
receives external signal
20
and converts the same to a flash memory control signal group
13
that can control flash memory
6
. The converted signal is output to selector
11
. DLC
48
also converts the signal in control signal group
14
of the flash memory received from flash memory
6
into a predetermined format and provides the converted signal as external signal
20
for the DLC.
Since BIU
2
is in synchronization with the operation of CPU
1
during memory access at the time of non-reset, an ACK (complete) signal is output to CPU
1
via a signal group
18
when the process of access request from CPU
1
is completed.
FIG. 2
is a block diagram showing another example of a conventional microcomputer. This microcomputer allows data input/output with register group
3
, DRAM
4
, and SRAM
5
, via the DLC, in addition to flash memory
6
.
The microcomputer of
FIG. 2
differs from the microcomputer of
FIG. 1
in that selectors
30
,
31
and
32
are additionally provided between BIU
2
and each of register group
3
, DRAM
4
and SRAM
5
, respectively, and that a DLC
50
is provided instead of DLC
48
of FIG.
1
. DLC
50
generates and provides to selectors
30
-
32
a register group control signal group
27
, a DRAM control signal group
28
, and an SRAM control signal group
29
to control selectors
30
-
32
, in addition to flash memory control signal group
13
. In
FIG. 2
, components corresponding to those of
FIG. 1
have the same reference characters allotted. The function and labels thereof are identical. Therefore, detailed description thereof will not be repeated here.
Selectors
30
-
32
have a function similar to that of selector
11
to select which of signal groups
27
-
29
and bus group
12
is to be coupled to register group
3
, DRAM
4
and SRAM
5
.
The microcomputer can input/output data via DLC
50
with respect to register group
3
, DRAM
4
and SRAM
5
, in addition to flash memory
6
.
In the microcomputer of
FIG. 1
, only flash memory
6
can have data input/output via DLC
48
even though there are a plurality of memories. It is desirable to provide a microcomputer that can have data input/output with respect to an arbitrary memory.
The microcomputer of
FIG. 2
can have data input/output with respect to an arbitrary memory via DLC
50
. However, this microcomputer requires an DLC
50
that can generate and output individually a signal specified for each memory. For this purpose, the circuit area of DLC
50
is increased. The circuit area of the entire microcomputer is also increased since a selector has to be provided for each memory. It is to be noted that, when a plurality of memories are used, the access rate differs depending upon the type thereof. It is desirable to input/output data reliably and as fast as possible.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a microcomputer with a plurality of memories, including a DLC that can input/output data with respect to an arbitrary memory independent of control by a CPU, and without increasing the area of required circuitry.
Another object of the present invention is to provide a microcomputer with a plurality of memories, including a DLC that can input/output data with respect to an arbitrary memory during reset, without increasing the area of required circuitry.
A further object of the present invention is to provide a microcomputer with the plurality of memories, including a DLC that can reliably input/output data with respect to an arbitrary memory during reset, without increasing the area of required circuitry.
Still another object of the present invention is to provide a microcomputer with a plurality of memories, including a DLC that can input/output data with respect to an arbitrary memory during reset and also after reset, without increasing the area of required circuitry.
A microcomputer according to an aspect of the present invention includes a plurality of memories, a bus interface circuit connected to the plurality of memories through a bus group, a central processing unit to be connected to a plurality of memories via the bus interface circuit, and operating using the memories, a download circuit to be connected to the plurality of memories via the bus interface circuit, carry
Kanzaki Teruaki
Ueki Hiroshi
LandOfFree
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