Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-02-17
2003-02-25
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000
Reexamination Certificate
active
06525383
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a power MOSFET which includes a substrate with an upper main surface; a drain zone of a first conductivity type is embedded in the main surface and contacted by a drain electrode; a source zone of the first conductivity type is embedded in the main surface and contacted by a source electrode, the source zone is surrounded by a region of a second conductivity type; a region of the first conductivity type is lightly doped in comparison with the drain zone and extends from the drain zone in the direction of the source zone; and a gate electrode is seated above the main surface on an insulation layer and peripherally overlaps both the source zone and the lightly doped region.
One such power MOSFET is shown, for instance, in the book by R. Müller entitled “Bauelemente der Halbleiter-Elektronik” [Semiconductor Electronics Components], Fourth Edition, Berlin, 1991, pp. 165-167 and FIG. 3/19 therein. The power MOSFET, for instance, has a p-substrate, in which two n
+
-doped wells are embedded and spaced apart from one another, for forming a source zone and a drain zone. The source zone is surrounded by a p-doped well, in which a channel can develop.
The n
+
-doped drain zone is adjoined by an n-doped region. A gate electrode which is above the main surface of the substrate, is separated from the main surface of the substrate by an insulation layer. Edges of the gate electrode overlap both the source zone and the drain zone.
During operation of such high-voltage MOS components, problems leading to damage of the component can arise. One of the main problems is the generation of so-called hot charge carriers (“hot carriers” or “hot electrons”). Hot charge carriers occur particularly in MOS components of the kind in which a high voltage is applied between the drain and the source, or in other words including power MOS components. Given an existing high electrical field, the hot charge carriers can absorb so much energy that they overcome the semiconductor/oxide barrier of approximately 3.1 eV and thereby damage the oxide. As a result, the electrons inside the channel of the MOSFET are made capable of recovering enough energy to reach the insulation layer under the gate or in other words to get into the gate oxide. In the most harmless case, it worsens the component by changing its characteristics. In the worst case, it renders the component nonfunctional.
In order to solve that problem, it is known, for instance, from the book entitled “VLSI Technology”, McGraw-Hill, 1988, pp. 481, 482, to attach a lightly doped region to the drain zone in the direction of the gate electrode, wherein that region has the same conductivity type as the drain zone but is more lightly doped. Through the use of such a lightly doped region, the electrical field in the drain zone is reduced, and as a result the electrons are prevented from being injected energetically enough into the gate oxide.
That initial solution to the problem is described in detail below in conjunction with
FIG. 6
in terms of a previously known power MOSFET. The drain feedthrough in the JFET of the power MOSFET is attained solely by way of the length of the lightly doped region, which naturally markedly lessens the packing density of high-voltage MOS components.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a power MOSFET, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type, which has a high electric strength and which in comparison with the previous power MOSFET can be produced with a higher packing density on a silicon wafer. In other words, while the electric strength should remain the same, it should be possible to realize the power MOSFET with a smaller silicon surface area.
With the foregoing and other objects in view there is provided, in accordance with the invention, a power MOSFET, comprising a substrate with an upper main surface; a drain zone of a first conductivity type embedded in the main surface and disposed centrally in the substrate; a drain electrode contacting the drain zone; a source zone of the first conductivity type embedded in the main surface; a region of a second conductivity type surrounding the source zone; a source electrode contacting the source zone; a region of the first conductivity type being lightly doped in comparison with the drain zone, the lightly doped region extending from the drain zone in the direction of the source zone, the lightly doped region annularly surrounding the drain zone and annularly surrounded by the source zone; an insulation layer; and an annularly shaped gate electrode seated above the main surface on the insulation layer and having an inner edge peripherally overlapping the lightly doped region and an outer edge peripherally overlapping the source zone.
In accordance with another feature of the invention, the substrate is formed of a semiconductor material of the second conductivity type; the lightly doped region is embedded in the substrate; and the source zone is surrounded by the substrate.
In accordance with a further feature of the invention, the first conductivity type is n-doped and the second conductivity type is p-doped, or the first conductivity type is p-doped and the second conductivity type is n-doped.
In accordance with an added feature of the invention, the drain zone disposed centrally in the substrate has an oval contour with a deactivated strip portion.
In accordance with an additional feature of the invention, the strip portion is formed of an insulation layer having a thickness of greater than approximately 200 nm.
In accordance with yet another feature of the invention, at at least one of the lightly doped region, the gate electrode and the source zone is disposed in an oval or ellipse around the drain zone.
In accordance with a concomitant feature of the invention, the at least one of the annular structures has a circular-annular form or a polygonal form.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a power MOSFET, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 3624466 (1971-11-01), Schnable
patent: 3787962 (1974-01-01), Yoshida et al.
patent: 3909320 (1975-09-01), Gauge et al.
patent: 3967305 (1976-06-01), Zuleeg
patent: 4394674 (1983-07-01), Sakuma et al.
patent: 4876579 (1989-10-01), Davis et al.
patent: 5637891 (1997-06-01), Lee
“Bauelemente der Halbleiter-Elektronik”, Fourth Edition, Berlin, 1991, pp. 165-167.
“VLSI Technology”, McGraw-Hill, 1998, pp. 481-482.
Farahani Dana
Greenberg Laurence A.
Locher Ralph E.
Pham Long
Siemens Aktiengesellschaft
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